Research Subjects in Hiramoto Lab.

1. Device Improvement by Collaboration with Circuit Design


1.1. Post-Fabrication Self-Improvement of Transistor Variability


We have proposed a novel post-fabrication self-suppression technique of transistor variability [1,2]. We have found that the SRAM cell inherently has the self-suppression mechanism and the technique utilizes this mechanism. The technique utilizes the self-suppression mechanism. When high voltage is applied to the Vdd terminal of SRAM cell array, only stronger transistors are stressed and hence these transistors are weakened resulting in the cell stability improvement. The self-improvement of SRAM cells have been experimentally demonstrated [2,3]. This kind of post-fabrication technique with collaboration with circuit techniques will be promising for future VLSI.


[1]    M. Suzuki, T. Saraya, K. Shimizu, T. Sakurai, and T. Hiramoto, “Post-Fabrication Self-Convergence Scheme for Suppressing Variability in SRAM Cells and Logic Transistors”, Symposium on VLSI Technology, pp. 148 – 149, June 16, 2009.

[2]    M. Suzuki, T. Saraya, K. Shimizu, A. Nishida, S. Kamohara, K. Takeuchi, S. Miyano, T. Sakurai, and T. Hiramoto, “Direct Measurements, Analysis, and Post-Fabrication Improvement of Noise Margins in SRAM Cells Utilizing DMA SRAM TEG”, Symposium on VLSI Technology, pp. 191 – 192, June, 2010.

[3]    A. Kumar, T. Saraya, S. Miyano, and T. Hiramoto, “Self-Improvement of Cell Stability in SRAM by Post Fabrication Technique”, IEEE Silicon Nanoelectronics Workshop, pp. 79 80, June 10, 2012.


1.2. Low Power Devices Using Body Effect


The substrate bias is a powerful tool for achieving high performance and ultra-low power at the same time. We have proposed a new idea of “variable body factor” fully depleted SOI MOSFET utilizing depletion layer expansion and contraction. The devices have been fabricated, and the higher drive current and low-power operation have been demonstrated [1,2]. We also proposed device design guideline for 3D-structure FinFETs with sufficient body factor [3].


[1]    T. Ohtou, T. Saraya, K. Shimokawa, Y. Doumae, Y. Nagatomo, J. Ida and T. Hiramoto, “Experimental Demonstrations of Superior Characteristics of Variable Body-Factor (γ) Fully-Depleted SOI MOSFETs with Extremely Thin BOX of 10nm, IEEE International Electron Devices Meeting (IEDM), pp. pp. 877 – 880, December, 2006.

[2]    T. Ohtou, T. Saraya, and T. Hiramoto (Invited), “Variable Body-Factor SOI MOSFET with Ultrathin Buried Oxide for Adaptive Threshold Voltage and Leakage Control”, IEEE Transactions on Electron Devices, vol. 54, no. 1, pp. 40 – 46, January, 2008.

[3]    T. Nagumo and T. Hiramoto, “Design Guideline of Multi-Gate MOSFETs With Substrate-Bias Control”, IEEE Transactions on Electron Devices, Vol. 53, No. 12, pp. 3025 – 3031, December, 2006.


2. Device Physics and Variability


2.1. Variability in Scaled Transistors


As the transistor size is scaled down, the variability is one of the most significant problems for future device scaling and further reduction of supply voltage. In 2006 – 2011, “Robust Design of Transistor” Program has been conducted under the MIRAI Project supported by NEDO. The main achievements are the clarification of transistor variability origins and the development of new methodology for Vth variability [1,2]. We have analyzed SRAM cell stability using special device-matrix-array TEG and found that DIBL has a large impact of SRAM cell stability [3]. We also successfully measured Vth variability of 10 billion transistors [4]. Our group has a mass of variability data, and we have made many invited talks and tutorial presentations.


[1]    K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto, “Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies”, International Electron Devices Meeting (IEDM), pp. 467 – 470, December, 2007.

[2]    A. T. Putra, T. Tsunomura, A. Nishida, S. Kamohara, K. Takeuchi, S. Inaba, K. Terada, and T. Hiramoto, “A New Methodology for Evaluating VT Variability Considering Dopant Depth Profile”, Symposium on VLSI Technology, pp. 116 – 117, June, 2009.

[3]    X. Song, M. Suzuki, T. Saraya, A. Nishida, T. Tsunomura, S. Kamohara, K. Takeuchi, S. Inaba, T. Mogami, and T. Hiramoto, “Impact of DIBL Variability on SRAM Static Noise Margin Analyzed by DMA SRAM TEG”, International Electron Devices Meeting (IEDM), pp. 62 – 65, December, 2010.

[4]    T. Mizutani, A. Kumar, and T. Hiramoto, “Measuring Threshold Voltage Variability of 10G Transistors”, International Electron Devices Meeting (IEDM), pp. 563 – 566, December, 2011.


2.2. Quantum Effects in Nano-Scaled Silicon MOSFETs


When transistor size is scaled down to the nanometer regime, quantum effect appears and affects the device characteristics. The purpose of this work is to elucidate the effects of quantum effects in nanometer silicon devices and utilize these effects for higher performance and lower energy dissipation. We have found for the first time that (110) nFETs with very thin SOI channel have higher electron mobility due to volume inversion at double-gate operation [1]. We have also elucidated the origins of high hole mobility and strain effects in (110) pFETs [2,3].


[1]    G. Tsutsui, M. Saitoh, T. Saraya, T. Nagumo, and T. Hiramoto, “Mobility Enhancement due to Volume Inversion in (110)-oriented Ultra-thin Body Double-gate nMOSFETs with Body Thickness less than 5 nm”, International Electron Devices Meeting (IEDM), pp. 747 - 750, December, 2005.

[2]    K. Shimizu, T. Saraya and T. Hiramoto, “Experimental Investigation on the Origin of Direction Dependence of Si (110) Hole Mobility Utilizing Ultra-Thin Body pMOSFETs”, IEEE International Electron Devices Meeting (IEDM), pp. 67 – 70, December, 2008.

[3]    K. Shimizu, T. Saraya, and T. Hiramoto, “Physical Understandings of Si (110) Hole Mobility in Ultra-Thin Body pFETs by <110> and <111> Uniaxial Compressive Strain”, International Electron Devices Meeting (IEDM), pp. 473 – 476, December 8, 2009.


2.3. Silicon Nanowire Transistors


Silicon nanowire transistor is a promising device due to high short-channel effect immunity and higher performance. Our group demonstrated the quantum effects in silicon nanowire transistors for the first time in 1999 [1] and mobility enhancement in silicon nanowire in 2001 [2]. These are pioneering works in the field of nanowire transistors. The width of nanowire is less than 5nm. Recently, we successfully develop a method to evaluate nanowire mobility precisely [3] and found for the first time that hole mobility exceeds the universal hole mobility in (100) silicon nanowire pFETs [4].


[1]    H. Majima, H. Ishikuro, and T. Hiramoto, “Threshold Voltage Increase by Quantum Mechanical Narrow Channel Effect in Ultra-Narrow MOSFETs”, International Electron Devices Meeting (IEDM), pp. 379 - 382, December, 1999.

[2]    H. Majima, Y. Saito, and T. Hiramoto, “Impact of Quantum Mechanical Effects on Design of Nano-Scale Narrow Channel n- and p-type MOSFETs”, International Electron Devices Meeting (IEDM), pp. 733 - 736, December, 2001.

[3]    J. Chen, T. Saraya, K. Miyaji, K. Shimizu, and T. Hiramoto, “Experimental Study of Mobility in [110]- and [100]-Directed Multiple Silicon Nanowire GAA MOSFETs on (100) SOI”, Symposium on VLSI Technology, pp. 32 – 33, June, 2008.

[4]    J. Chen, T. Saraya, and T. Hiramoto, “Mobility Enhancement over Universal Mobility in (100) Silicon Nanowire Gate-All-Around MOSFETs with Width and Height of Less Than 10nm Range”, VLSI Symposium on Technology, pp. 175 – 176, June, 2010.


3. Nano Devices and New Functionality


3.1. Silicon Single Electron Transistors and Integration with VLSI


Single-electron transistor (SET) is one of the so-called Beyond CMOS devices. In this study, room temperature operation of SETs is pursued and circuit applications of SETs are discussed. We successfully fabricated silicon SETs and observed the Coulomb blockade oscillations with peak-to-valley current ratio of as high as 400 at room temperature [1]. We also observe a new functional behavior of parallel shift of Coulomb oscillations and negative differential conductance due to quantum confinement effect in a silicon dot [2]. On the other hand, analog pattern matching has been demonstrated using three integrated SETs at room temperature [3], and SETs have been successfully integrated with CMOS circuits for higher functionality [4].


[1]    K. Miyaji, M. Saitoh, and T. Hiramoto, “Voltage gain dependence of the negative differential conductance width in silicon single-hole transistors”, Applied Physics Letters, Vol. 88, No. 14, 143505, April, 2006.

[2]    S. Lee, K. Miyaji, M. Kobayashi, and T. Hiramoto, “Extremely high flexibilities of Coulomb blockade and negative differential conductance oscillations in room-temperature-operating silicon single hole transistor”, Applied Physics Letters, vol. 92, no. 7, 073502, February, 2008.

[3]    M. Saitoh, H. Harata, and T. Hiramoto, “Room-Temperature Demonstration of Integrated Silicon Single-Electron Transistor Circuits for Current Switching and Analog Pattern Matching”, IEEE Electron Devices Meeting (IEDM), pp. 187 - 190, December, 2004.

[4]    R. Suzuki, M. Nozue, T. Saraya, and T. Hiramoto, “Integration of 1-bit CMOS Address Decoders and Single-Electron Transistors Operating at Room Temperature”, International Conference on Solid State Devices and Materials (SSDM), September, 2012.