International Journals

[160]Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, and Toshiro Hiramoto, “Parallel programmable nonvolatile memory using ordinary static random access memory cells”, Japanese Journal of Applied Physics, vol. 56, no.4S, 04CD17, March, 2017.
[159]Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, and Toshiro Hiramoto, “Correlation between static random access memory power-up state and transistor variation”, Japanese Journal of Applied Physics, vol. 56, no.4S, 04CD03, March, 2017.
[158]Masaharu Kobayashi, Kyungmin Jang, Nozomu Ueyama, and Toshiro Hiramoto, “Negative Capacitance for Boosting Tunnel FET Performance”, IEEE Transactions on Nanotechnology, vol. 16, no. 2, pp. 253 - 258, March, 2017.
[157]Hao Qiu, Kiyoshi Takeuchi, Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “Statistical Write Stability Characterization in SRAM Cells at Low Supply Voltage”, IEEE Transactions on Electron Devices, vol. 63, no. 11, pp. 4302 - 4308, November, 2016.
[156]Masahide Goto, Kei Hagiwara, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Pixel-Parallel CMOS Image Sensors with 16-bit A/D Converters Developed by 3-D Integration of SOI Layers with Au/SiO2 Hybrid Bonding”, ECS Transactions, vol. 72, no. 3, pp. 3 – 6, May, 2016.
[155]Tomoko Mizutani, Takuya Saraya, Kiyoshi Takeuchi, Masaharu Kobayashi, and Toshiro Hiramoto, “Transistor-level characterization of static random access memory bit failures induced by random telegraph noise”, Japanese Journal of Applied Physics, vol. 55, no.4S, 04ED05, March, 2016.
[154]Masaharu Kobayashi and Toshiro Hiramoto, “On device design for steep-slope negative-capacitance field-effect-transistor operating at sub-0.2V supply voltage with ferroelectric HfO2 thin film”, AIP Advances, vol. 6, no. 2, 025113, February, 2016.
[153]Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Pixel-Parallel 3-D Integrated CMOS Image Sensors with Pulse-Frequency-Modulation A/D Converters Developed by Direct Bonding of SOI Layers”, IEEE Transactions on Electron Devices, Vol. 62, No. 11, pp. 3530 – 3535, November, 2015.
[152]Kosmas Galatsis, Paolo Gargini, Toshiro Hiramoto, Dirk Beernaert, Roger DeKeersmaecker, Joachim Pelka, and Lothar Pfitzner, “Nanoelectronics Research Gaps and Recommendations, A Report from the International Planning Working Group on Nanoelectronics (IPWGN)”, IEEE Technology and Society Magazine, Vol. 34, No. 2, pp. 21 – 30, June, 2015.
[151]Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, and Toshiro Hiramoto, “Detailed analysis of minimum operation voltage of extraordinarily unstable cells in fully depleted silicon-on-buried-oxide six-transistor static random access memory”, Japanese Journal of Applied Physics, vol. 54, no.4S, 04DC16, March, 2015.
[150]Hao Qiu, Tomoko Mizutani, Takuya Saraya, and Toshiro Hiramoto, “Comparison and statistical analysis of four write stability metrics in bulk CMOS static random access memory cells”, Japanese Journal of Applied Physics, vol. 54, no.4S, 04DC09, March, 2015.
[149]Youngmin Lee, Sejoon Lee, Hyunsik Im, and Toshiro Hiramoto, “Multiple logic functions from extended blockade region in a silicon quantum-dot transistor”, Journal of Applied Physics, vol. 117, no.6, 064501, February, 2015.
[148]Seung-Min Jung, Tomoko Mizutani, and Toshiro Hiramoto, “Effect of drain-induced barrier lowering on performance of ultralow-supply-voltage CMOS circuits operating in subthreshold region”, Japanese Journal of Applied Physics, Vol. 53, No. 12, 124301, December, 2014.
[147]Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “3-D Silicon-on-Insulator Integrated Circuits With NFET and PFET on Separate Layers Using Au/SiO2 Hybrid Bonding”, IEEE Transactions on Electron Devices, vol. 61, no.8, pp. 2886 – 2892, August, 2014.
[146]Nurul Ezaila Alias, Anil Kumar, Takuya Saraya, and Toshiro Hiramoto, “Threshold Voltage Shifts and Their Variability Behaviors in pFETs by High Voltage ON-State and OFF-State Stress”, Japanese Journal of Applied Physics, Vol. 53, No. 8S1, 08LC01, August, 2014.
[145]Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Development of Novel Three-Dimensional Structuring of Integrated Circuits by Using Low Temperature Direct Bonding for CMOS Image Sensors”, ECS Transactions, Vol. 61, Issue 6, pp. 87 – 90, May, 2014.
[144]Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Hiroshi Toshiyoshi, Toshiro Hiramoto, “A Novel MOSFET with Vertical Signal-Transfer Capability for 3D-Structured CMOS Image Sensors”, IEEJ Transactions on Electrical and Electronic Engineering, Vol. 9, Issue 3, pp. 329 –333, April, 2014.
[143]Nobuyuki Sugii, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi, Koichiro Ishibashi, Tomoko Mizutani, and Toshiro Hiramoto, “Ultralow-power SOTB CMOS Technology Operating Down to 0.4 V”, Journal of Low Power Electronics and Applications, Vol. 4, pp. 65 - 76, April, 2014.
[142]Yuma Tanahashi, Ryota Suzuki, Takuya Saraya, Toshiro Hiramoto, “Peak Position Control of Coulomb Blockade Oscillations in Silicon Single-Electron Transistors with Floating Gate Operating at Room Temperature”, Japanese Journal of Applied Physics, Vol. 53, No. 4S, 04EJ08, March, 2014.
[141]Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii, and Toshiro Hiramoto, “Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells”, Japanese Journal of Applied Physics, Vol. 53, No. 4S, 04EC18, March, 2014.
[140]Youngmin Lee, Sejoon Lee, and Toshiro Hiramoto, “Transport behaviors and mechanisms in cuspidal blockade region for silicon single-hole transistor”, Current Applied Physics, vol. 14, no. 3, pp. 428 – 432, March, 2014.
[139]Qi Wang, Yaomi Itoh, Tohru Tsuruoka, Tsuyoshi Hasegawa, Satoshi Watanabe, Shu Yamaguchi, Toshiro Hiramoto, and Masakazu Aono, “Two types of on-state observed in the operation of a redox-based three-terminal device”, Key Engineering Materials, Vol. 596, pp. 111 – 115, January, 2014.
[138]Sejoon Lee, Youngmin Lee, Emil B. Song, and Toshiro Hiramoto, “Observation of Single Electron Transport via Multiple Quantum States of a Silicon Quantum Dot at Room Temperature”, Nano Letters, Vol. 14, No. 1, pp. 71 – 77, January, 2014.
[137]Sejoon Lee, Youngmin Lee, Emil B. Song, and Toshiro Hiramoto, “The characteristic of elongated Coulomb-blockade regions in a Si quantum-dot device coupled via asymmetric tunnel barriers”, Journal of Applied Physics, vol. 114, no. 16, 164513, October, 2013.
[136]Ryota Suzuki, Motoki Nozue, Takuya Saraya, and Toshiro Hiramoto, “Experimental Observation of Quantum Confinement Effect in (110) and (100) Silicon Nanowire Field-Effect Transistors and Single-Electron/Hole Transistors Operating at Room Temperature”, Japanese Journal of Applied Physics, Vol. 52, No. 10, 104001, October, 2013.
[135]Sejoon Lee, Youngmin Lee, Emil B. Song, and Toshiro Hiramoto, “Modulation of peak-to-valley current ratio of Coulomb blockade oscillations in Si single hole transistors”, Applied Physics Letters, vol. 103, no. 10, 103502, September, 2013.
[134]Motoki Nozue, Ryota Suzuki, Hirotoshi Nomura, Takuya Saraya, and Toshiro Hiramoto, “Characteristics Control of Room-Temperature Operating Single Electron Transistor with Floating Gate by Charge Pump Circuit”, Solid State Electronics, Vol. 88, pp. 61 – 64, October, 2013.
[133]Qi Wang, Yaomi Itoh, Tsuyoshi Hasegawa, Tohru Tsuruoka, Shu Yamaguchi, Satoshi Watanabe, Toshiro Hiramoto, and Masakazu Aono, “Nonvolatile three-terminal operation based on oxygen vacancy drift in a Pt/Ta2O52x/Pt, Pt structure”, Applied Physics Letters, vol. 102, no. 23, 233508, June, 2013.
[132]Toshiro Hiramoto, Anil Kumar, Takuya Saraya, and Shinji Miyano (Invited), “Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress”, IEICE Transactions on Electronics, Vol. E96-C, No. 6, pp. 759 – 765, June, 2013.
[131]Tomoko Mizutani, Anil Kumar, and Toshiro Hiramoto, “Statistical Analysis of Current Onset Voltage (COV) Distribution of Scaled MOSFETs”, IEICE Transactions on Electronics, Vol. E96-C, No. 5, pp. 630 – 633, May, 2013.
[130]Nurul Ezaila Alias, Anil Kumar, Takuya Saraya, Shinji Miyano, and Toshiro Hiramoto, “NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM”,IEICE Transactions on Electronics, Vol. E96-C, No. 5, pp. 620 – 623, May, 2013.
[129]Ryota Suzuki, Motoki Nozue, Takuya Saraya and Toshiro Hiramoto, “Integration of Complementary Metal-Oxide-Semiconductor 1-Bit Analog Selectors and Single-Electron Transistors Operating at Room Temperature”, Japanese Journal of Applied Physics, Vol. 52, No. 4, 04CJ05, March, 2013.
[128]Ke Mao, Takuya Saraya, and Toshiro Hiramoto, “Effects of Side Surface Roughness on Carrier Mobility in Tri-Gate Single Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect Transistors”, Japanese Journal of Applied Physics, Vol. 52, No. 4, 04CC11, March, 2013.
[127]Ke Mao, Takuya Saraya, and Toshiro Hiramoto, “Direct Measurement of Carrier Mobility in Intrinsic Channel Tri-Gate Single Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect Transistors”, Japanese Journal of Applied Physics, Vol. 52, No. 4, 04CC08, March, 2013.
[126]Sejoon Lee, Youngmin Lee, Emil B. Song, Kang L. Wang, and Toshiro Hiramoto, “Gate-tunable selective operation of single electron/hole transistor modes in a silicon single quantum dot at room temperature”, Applied Physics Letters, Vol. 102, No. 8, 083504, February, 2013.
[125]Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii, and Toshiro Hiramoto, “Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-Buried-Oxide and Bulk Metal-Oxide-Semiconductor Field Effect Transistors”, Japanese Journal of Applied Physics, Vol. 52, No. 4, 04CC02, February, 2013.
[124]Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Development of Novel MOSFET with Front and Back Side Electrodes for 3D-structured Image Sensors”, ECS Transactions, Vol. 50, No. 14, pp. 49 – 54, December, 2012.
[123]Ke Mao, Tomoko Mizutani, Anil Kumar, Takuya Saraya, and Toshiro Hiramoto,"Suppression of Within-Device Variability in Intrinsic Channel Tri-Gate Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect Transistors",Japanese Journal of Applied Physics, Vol. 51, No. 2, 02BC06, February, 2012
[122]Anil Kumar, Tomoko Mizutani, and Toshiro Hiramoto, "Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors", Japanese Journal of Applied Physics, Vol. 51, No. 2, 024106, February, 2012.
[121]Toshiro Hiramoto, Makoto Suzuki, Xiaowei Song, Ken Shimizu, Takuya Saraya, Akio Nishida, Takaaki Tsunomura, Shiro Kamohara, Kiyoshi Takeuchi, and Tohru Mogami (Invited), "Direct Measurement of Correlation Between SRAM Noise Margin and Individual Cell Transistor Variability by Using Device Matrix Array", IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2249 - 2256, August, 2011.
[120]Takaaki Tsunomura, Anil Kumar, Tomoko Mizutani, Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara, Kazuo Terada, Toshiro Hiramoto, and Tohru Mogami, "High-Temperature Properties of Drain Current Variability in Scaled Field-Effect Transistors Analyzed by Decomposition Method", Japanese Journal of Applied Physics, Vol. 50, No. 4, 04DC08, April, 2011.
[119]Toshiro Hiramoto, Takuya Saraya, and Chiho Lee, "Effect of Back Bias on Variability in Intrinsic Channel SOI MOSFETs", Key Engineering Materials, Vol. 470, Special Issue on Technology Evolution for Silicon Nano-Electronics, pp. 214 - 217, February, 2011.
[118]Takaaki Tsunomura, Akio Nishida, and Toshiro Hiramoto, "Effect of Channel Dopant Profile on Difference in Threshold Voltage Variability Between NFETs and PFETs", IEEE Transactions on Electron Devices, Vol. 58, No. 2, pp. 364 - 369, February, 2011.
[117]Michel Brillouet, George I. Bourianoff, Ralph Keary Cavin, III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, and Ken Uchida, "Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps", Proceedings of the IEEE, Vol. 98, No. 12, pp. 1993 - 2004, December, 2010.
[116]Jiezhi Chen, Takuya Saraya, and Toshiro Hiramoto, "Hole Mobility Characteristics in Si Nanowire pMOSFETs on (110) Silicon-On-Insulator", IEEE Electron Devices Letters, vol. 31, No. 11, pp. 1181 - 1183, November, 2010.
[115]Takaaki Tsunomura, Anil Kumar, Tomoko Mizutani, Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara, Kazuo Terada, Toshiro Hiramoto, and Tohru Mogami, "Origin of Larger Drain Current Variability in N-Type Field-Effect Transistors Analyzed by Variability Decomposition Method", Applied Physics Express, Vol. 3, No. 11, 114201, November, 2010.
[114]Takaaki Tsunomura, Fumiko Yano, Akio Nishida, and Toshiro Hiramoto, "Possible Origins of Extra Threshold Voltage Variability in N-Type Field-Effect Transistors by Intentionally Changing Process Conditions and Using Takeuchi Plot", Japanese Journal of Applied Physics, Vol. 49, No. 7, 074104, July, 2010.
[113]Ken Shimizu, Takuya Saraya, and Toshiro Hiramoto, "Superior <110>-Directed Electron Mobility to <100>-Directed Electron Mobility in Ultrathin Body (110) n-Type Metal-Oxide-Semiconductor Field-Effect Transistors", Japanese Journal of Applied Physics, Vol. 49, No. 5, 051303, May, 2010.
[112]Takaaki Tsunomura, Akio Nishida, and Toshiro Hiramoto, "Investigation of Threshold Voltage Variability at High Temperature Using Takeuchi Plot", Japanese Journal of Applied Physics, Vol. 49, No. 5, 054101, May, 2010.
[111]Chiho Lee, Arifin Tamsir Putra, Ken Shimizu and Toshiro Hiramoto, "Threshold Voltage Dependence of Threshold Voltage Variability in Intrinsic Channel Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors with Ultrathin Buried Oxide", Japanese Journal of Applied Physics, Vol. 49, No. 4, Issue 2, 04DC01, April, 2010.
[110]Ken Shimizu and Toshiro Hiramoto, "Mobility Degradation in (110)-Oriented Ultrathin-Body Double-Gate p-Type Metal-Oxide-Semiconductor Field-Effect Transistors with Silicon-on-Insulator Thickness of Less than 5 nm", Japanese Journal of Applied Physics, Vol. 49, No. 4, 041302, April, 2010.
[109]Ken Shimizu, Takuya Saraya, and Toshiro Hiramoto, "Suppression of Electron Mobility Degradation in (100)-Oriented Double-Gate Ultrathin Body nMOSFETs", IEEE Electron Devices Letters, vol. 31, No. 4, pp. 284 - 286, April, 2010.
[108]Takaaki Tsunomura, Akio Nishida, and Toshiro Hiramoto, "Verification of Threshold Voltage Variation Properties in Scaled Transistors with Ultra Large-Scale Device Matrix Array Test Element Group", Japanese Journal of Applied Physics, Vol. 48, No. 12, 124505, December, 2009.
[107]Jiezhi Chen, Takura Saraya, and Toshiro Hiramoto, "Experimental Investigations of Electron Mobility in Silicon Nanowire nMOSFETs on (110) Silicon-on-Insulator", IEEE Electron Devices Letters, vol. 30, No, 11, pp. 1203 - 1205, November, 2009.
[106]Takaaki Tsunomura, Akio Nishida, and Toshiro Hiramoto, "Analysis of NMOS and PMOS Difference in VT Variation with Large-Scale DMA-TEG", IEEE Transactions on Electron Devices, Vol. 56, No. 9, pp. 2073 - 2080, September, 2009.
[105]Sanghoon Hwang, Hyunsik Im, Minkyu Song, Koichi Ishida, Toshiro Hiramoto, and Takayasu Sakurai, "Velocity Saturation Effects in a Short Channel Si-MOSFET and its Small Signal Characteristics", Journal of the Korean Physical Society, Vol. 55, No. 2, pp, 581 - 584, August, 2009.
[104]T. Ishigaki, R. Tsuchiya, Y. Morita, H. Yoshimoto, N. Sugii, T. Iwamatsu, H. Oda Y. Inoue, T. Ohtou, T. Hiramoto, and S. Kimura, "Silicon on Thin BOX (SOTB) CMOS for Ultralow Standby Power with Forward-biasing Performance Booster", Solid State Electronics, pp. 717 - 722, July, 2009.
[103]Arifin Tamsir Putra, Takaaki Tsunomura, Akio Nishida, Shiro Kamohara, Kiyoshi Takeuchi, and Toshiro Hiramoto, "Impact of Oxide Thickness Fluctuation and Local Gate Depletion on Threshold Voltage Variation in Metal-Oxide-Semiconductor Field-Effect-Transistors", Japanese Journal of Applied Physics, Vol. 48, No. 6, 064504, June, 2009.
[102]YeonJoo Jeong, Kousuke Miyaji, Takuya Saraya, and Toshiro Hiramoto, "Silicon nanowire n-type metal-oxide-semiconductor field-effect-transistors and single-electron transistors at room temperature under uniaxial tensile strain", Journal of Applied Physics, Vol. 105, No. 8, April, 2009.
[101]Nobuyuki Sugii, Ryuta Tsuchiya, Takashi Ishigaki, Yusuke Morita, Hiroyuki Yoshimoto, Toshiaki Iwamatsu, Hidekazu Oda, Yasuo Inoue, Toshiro Hiramoto, and Shin'ichiro Kimura, "Evaluation of Threshold-Voltage Variation in Silicon on Thin Buried Oxide Complementary Metal-Oxide-Semiconductor and Its Impact on Decreasing Standby Leakage Current", Japanese Journal of Applied Physics, Vol. 48, No. 4, 04C043, April, 2009.
[100]Arifin Tamsir Putra, Akio Nishida, Shiro Kamohara, Takaaki Tsunomura, and Toshiro Hiramoto, "Consideration of Random Dopant Fluctuation Models for Accurate Prediction of Threshold Voltage Variation of Metal-Oxide-Semiconductor Field-Effect Transistors in 45nm Technology and Beyond", Japanese Journal of Applied Physics, Vol. 48, No. 4, 044502, April, 2009.
[99]T. Hiramoto, J. Chen, Y.J. Jeong, and T. Saraya, "Transport in Silicon Nanowire Transistors", ECS Transactions, Vol. 18, No. 1, pp. 55 - 60, March, 2009.
[98]Arifin Tamsir Putra, Akio Nishida, Shiro Kamohara, and Toshiro Hiramoto, "Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal-Oxide-Semiconductor Field-Effect Transistors", Applied Physics Express, Vol. 2, No. 2, 024501, January, 2009.
[97]Jiezhi Chen, Takura Saraya, Kousuke Miyaji, Ken Shimizu, and Toshiro Hiramoto, "Electron Mobility in Silicon Gate-All-Around [100]- and [110]-Directed Nanowire Metal-Oxide-Semiconductor Field-Effect Transistor on (100)-Oriented Silicon-on-Insulator Substrate Extracted by Improved Split Capacitance-Voltage Method", Japanese Journal of Applied Physics, Vol. 48, No. 1, 011205, January, 2009.
[96]Sejoon Lee and Toshiro Hiramoto, "Strong dependence of tunneling transport properties on over-driving voltage for room-temperature-operating single electron/hole transistors formed with ultra narrow [100] silicon nanowire channel", Applied Physics Letters, vol. 93, No. 4, 043508, July, 2008.
[95]Takashi Ishigaki, Ryuta Tsuchiya, Yusuke Morita, Nobuyuki Sugii, Shinichiro Kimura, Toshiaki Iwamatsu, Takashi Ipposhi, Yasuo Inoue, and Toshiro Hiramoto, "Wide-Range Threshold Voltage Controllable Silicon on Thin Buried Oxide Integrated with Bulk Complementary Metal Oxide Semiconductor Featuring Fully Silicided NiSi Gate Electrode", Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2585 - 2588, April, 2008.
[94]Masaharu Kobayashi, Kousuke Miyaji, and Toshiro Hiramoto, "On the Origin of Negative Differential Conductance in Ultranarrow Wire Channel Silicon Single-Electron and Single-Hole Transistor", Japanese Journal of Applied Physics, vol. 47, no. 3, pp. 1813 - 1817, March, 2008.
[93]Masaharu Kobayashi and Toshiro Hiramoto, "Experimental Study on Quantum Confinement Effects in Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect-Transistors and Single-Electron Transistors", Journal of Applied Physics, vol. 103, no. 5, 053709, March, 2008.
[92]Sejoon Lee, Kousuke Miyaji, Masaharu Kobayashi, and Toshiro Hiramoto, "Extremely high flexibilities of Coulomb blockade and negative differential conductance oscillations in room-temperature-operating silicon single hole transistor", Applied Physics Letters, vol. 92, no. 7, 073502, February, 2008.
[91]Tetsu Ohtou, Takuya Saraya, and Toshiro Hiramoto (Invited), "Variable Body-Factor SOI MOSFET with Ultrathin Buried Oxide for Adaptive Threshold Voltage and Leakage Control", IEEE Transactions on Electron Devices, vol. 54, no. 1, pp. 40 - 46, January, 2008.
[90]T. Hiramoto (Invited), "Transport in Ultrathin SOI MOSFETs and Silicon Nanowire Transistors", ECS Transactions, Vol. 11, No. 6, ULSI Process Integration 5, pp. 403 - 411, October, 2007.
[89]Gen Tsutsui and Toshiro Hiramoto, "Experimental Study on Mobility in (110)-Oriented Ultrathin-Body Silicon-on-Insulator n-Type Metal Oxide Semiconductor Field-Effect Transistor with Single- and Double-Gate Operations", Japanese Journal of Applied Physics, Vol. 46, No. 9A, pp. 5686 - 5690, September, 2007.
[88]Tetsu Ohtou, Nobuyuki Sugii, and Toshiro Hiramoto, "Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX", IEEE Electron Devices Letters, Vol. 28, No. 8, pp. 740 - 742, August, 2007.
[87]Kousuke Miyaji and Toshiro Hiraoto, "Control of full width at half maximum of Coulomb oscillation in silicon single-hole transistors at room temperature", Applied Physics Letters, Vol. 91, No. 5, 053509, July, 2007.
[86]Ken Shimizu, Gen Tsutsui, and Toshiro Hiramoto, "Experimental Study on Mobility Universality in (100) Ultra Thin Body nMOSFET with SOI Thickness of 5nm", Japanese Journal of Applied Physics, Vol. 46, No. 20, pp. L480 - L482, May, 2007.
[85]K. Shimizu, G. Tsutsui, D. Januar, T. Saraya, and T. Hiramoto, "Experimental Study on Breakdown of Mobility Universality in <100>-directed (110)-oriented pMOSFETs". IEEE Transactions on Nanotechnology, Vol. 6, No. 3, pp. 358 - 361, May, 2007.
[84]Toshiro Hiramoto, Toshiharu Nagumo, Tetsu Ohtou, and Kouki Yokoyama (Invited), "Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations", IEICE Transactions on Electronics, Vol. E90-C, No. 4, pp. 836 - 841, April, 2007.
[83]T. Ohtou, K. Yokoyama, K. Shimizu, T. Nagumo, and T. Hiramoto, "Threshold-Voltage Control of AC Performance Degradation-Free FD SOI MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme", IEEE Transactions on Electron Devices, Vol. 54, No. 2, pp. 301 - 307, February, 2007.
[82]M. Kobayashi and T. Hiramoto, "Large Coulomb-Blockade Oscillations and Negative Differential Conductance in Silicon Single-Electron Transistors with [100]- and [110]- Directed Channels at Room Temperature", Japanese Journal of Applied Physics, Vol. 46, No. 1, pp. 24 - 27, January, 2007.
[81]T. Nagumo and Toshiro Hiramoto, "Design Guideline of Multi-Gate MOSFETs With Substrate-Bias Control", IEEE Transactions on Electron Devices, Vol. 53, No. 12, pp. 3025 - 3031, December, 2006.
[80]G. Tsutsui and T. Hiramoto, "Mobility and Threshold-Voltage Comparison Between (110)- and (100)-Oriented Ultrathin-Body Silicon MOSFETs ", IEEE Transactions on Electron Devices, Vol. 53, No. 10, pp. 2582 - 2588, October, 2006.
[79]T. Hiramoto, M. Saitoh, and G. Tsutsui, "Emerging nanoscale silicon devices taking advantage of nanostructure physics", IBM Journal of Research and Development, Vol. 50, No. 4/5, pp. 411 - 418, July/September, 2006.
[78]A. T. Putra, M. Saitoh, G. Tsutsui, and T. Hiramoto, " Modeling of Body Factor and Subthreshold Swing in Bulk Metal Oxide Semiconductor Field Effect Transistors in Short-Channel Regime", Japanese Journal of Applied Physics, Vol. 45, No. 8A, pp. 6173 - 6176, August, 2006.
[77]M. Kobayashi, M. Saitoh, and T. Hiramoto, "Large Temperature Dependence of Coulomb Blockade Oscillations in Room-Temperature-Operating Silicon Single-Hole Transistor", Japanese Journal of Applied Physics, Vol. 45, No. 8A, pp. 6157 - 6161, August, 2006.
[76]K. Miyaji, M. Saitoh, and T. Hiramoto, "Compact Analytical Model for Room-Temperature Operating Silicon Single-Electron Transistors with Discrete Quantum Energy Levels", IEEE Transactions on Nanotechnology, Vol. 5, No. 3, pp. 167 - 173, June, 2006.
[75]K. Miyaji, M. Saitoh, and T. Hiramoto, "Voltage gain dependence of the negative differential conductance width in silicon single-hole transistors", Applied Physics Letters, Vol. 88, No. 14, 143505, April, 2006.
[74]Sangsu Park, Hyunsik Im, Ilgweon Kim, and Toshiro Hiramoto, "Impact of Drain Induced Barrier Lowering on Read Scheme in Silicon Nanocrystal Memory with Two-Bit-per-Cell Operation", Japanese Journal of Applied Physics, Vol. 45, No. 2A, pp. 638 - 642, February, 2006.
[73]Gen Tsutsui, Masumi Saitoh, and Toshiro Hiramoto, "Experimental Study on Superior Mobility in (110)-Oriented UTB SOI pMOSFETs", IEEE Electron Devices Letters, Vol. 26, No. 11, pp. 836 - 838, November, 2005.
[72]Anil Kumar, Toshiharu Nagumo, Gen Tsutsui, Tetsu Ohtou, Toshiro Hiramoto, "Body factor conscious modeling of single gate fully depleted SOI MOSFETs for low power applications", Solid-State Electronics, Volume 49, Issue 6, June 2005, pp. 997 - 1001, July, 2005.
[71]Kosuke Yanagidaira, Masumi Saitoh, and Toshiro Hiramoto, "Enhancement of Charge Storage Performance in Double-Gate Silicon Nanocrystal Memories With Ultrathin Body Structure", IEEE Electron Devices Letters, Vol. 26, No. 7, pp. 473 - 475, July, 2005.
[70]Tetsu Ohtou, Toshiharu Nagumo, and Toshiro Hiramoto, "Short Channel Characteristics of Variable Body Factor FD SOI MOSFETs", Japanese Journal of Applied Physics, Vol. 44, No. 6A, pp. 3885 - 3888, June, 2005.
[69]Gen Tsutsui, Masumi Saitoh, Toshiharu Nagumo, and Toshiro Hiramoto, "Experimental Study on the Universality of Mobility Behavior in Ultra Thin Body SOI pMOSFETs", Vol. 44, No. 6A, pp. 3889 - 3892, June, 2005.
[68]Julien Brault, Masumi Saitoh, and Toshiro Hiramoto, "Channel Width and Length Dependence in Si NanoCrystal Memories with Ultra-NanoScale Channel", IEEE Transactions on Nanotechnology, Vol. 4, No. 3, pp. 349-354, May, 2005.
[67]Gen Tsutsui, Masumi Saitoh, Toshiharu Nagumo, and Toshiro Hiramoto, "Impact of SOI Thickness Fluctuation on Threshold Voltage Variation in Ultra Thin Body SOI MOSFETs", IEEE Transactions on Nanotechnology, Vol. 4, No. 3, pp. 369 - 373, May, 2005.
[66]Hidehiro Harata, Masumi Saitoh, and Toshiro Hiramoto, "Silicon Single-Hole Transistor with Large Coulomb Blockade Oscillations and High Voltage Gain at Room Temperature", Japanese Journal of Applied Physics, Vol. 44, Part 2, No. 20, pp. L640 - L642, May, 2005.
[65]Kosuke Yanagidaira, Masumi Saitoh, and Toshiro Hiramoto, "Effects of Channel Thinning on Threshold Voltage Shift in Ultrathin Body Silicon Nanocrystal Memories", Japanese Journal of Applied Physics, Vol. 44, Part 1, No. 4B, pp. 2608 - 2611, April, 2005.
[64]Fumihiko Tachibana and Toshiro Hiramoto, "Re-examination of Impact of Intrinsic Dopant Fluctuations on SRAM Static Noise Margin", Japanese Journal of Applied Physics, Vol. 44, Part 1, No. 4B, pp. 2147 - 2151, April, 2005.
[63]Kousuke Miyaji, Masumi Saitoh, Toshiharu Nagumo, and Toshiro Hiramoto, "Temperature Dependence of Off-Current in Bulk and FD SOI MOSFETs", Japanese Journal of Applied Physics, Vol. 44, Part 1, No. 4B, pp. 2371 - 2375, April, 2005.
[62]Masumi Saitoh, Hidehiro Harata and Toshiro Hiramoto, "Room-Temperature Operation of Current Switching Circuit Using Integrated Silicon Single-Hole Transistors", Japanese Journal of Applied Physics, Vol. 44, No. 11, pp. L338 - L341, February, 2005.
[61]Toshiharu Nagumo and Toshiro Hiramoto, "Reverse Short-Channel Effect of Body Factror in Low-Fin Field-Effect Transistors Induced by Corner Effect", Japanese Journal of Applied Physics, Vol. 44, No. 1A, pp. 50 - 54, January, 2005.
[60] Masumi Saitoh, Hidehiro Harata, and Toshiro Hiramoto, "Room-Temperature Demonstration of Low-Voltage and Tunable Static Memory Based on Negative Differential Conductance in Silicon Single-Electron Transistors", Applied Physics Letters, Vol. 85, No. 25, pp. 6233 - 6235, December, 2004.
[59]Anil Kumar, Toshiharu Nagumo, Gen Tsutsui, and Toshiro Hiramoto, "Analytical Model of Body Factor in Short Channel Bulk MOSFETs for Low Voltage Applications", Solid State Electronics, Vol. 48, No. 10-11, p. 1763 - 1766, October - November, 2004.
[58]Masumi Saitoh and Toshiro Hiramoto, "Room-temperature demonstration of highly-functional single-hole transistor logic based on quantum mechanical effect", IEE Electronics Letters, vol. 40, no. 13, pp. 837-838, July, 2004.
[57]Tetsu Ohtou, Toshiharu Nagumo, and Toshiro Hiramoto, "Variable Body Effect Factor Fully Depleted Silicon-On-Insulator Metal Oxide Semiconductor Field Effect Transistor for Ultra Low-Power Variable-Threshold-Voltage Complementary Metal Oxide Semiconductor Applications", Japanese Journal of Applied Physics, Vol. 43, No. 6A, pp. 3311 - 3314, June, 2004.
[56]I. Kim, K. Yanagidaira, and T. Hiramoto, "Scaling of Nano-Crystal Memory Cell by Direct Tungsten Bitline on Self-Aligned Landing Plug Polysilicon Contact", IEEE Electron Devices Letters, Vol. 25, No. 5, pp. 265 - 267, May, 2004.
[55]Masumi Saitoh and Toshiro Hiramoto, "Extension of Coulomb Blockade Region by Quantum Confinement in the Ultrasmall Silicon Dot in a Single-Hole Transistor at Room Temperature", Applied Physics Letters, Vol. 84, No. 16, pp. 3172 - 3174, April, 2004.
[54]Masumi Saitoh and Toshiro Hiramoto, "Room-Temperature Observation of Negative Differential Conductance Due to Large Quantum Level Spacing in Silicon Single-Electron Transistor", Japanese Journal of Applied Physics, Vol. 43, No. 2A, pp. L210 - L213, February, 2004.
[53]G. Tsutsui, T. Nagumo, and T. Hiramoto, "Enhancement of Adjustable Threshold Voltage Range by Substrate Bias Due to Quantum Confinement in Ultra Thin Body SOI pMOSFETs", IEEE Transactions on Nanotechnology, Vol. 2, No. 4, pp. 314 - 318, December, 2003.
[52]Masumi Saitoh, Tasuku Murakami, and Toshiro Hiramoto, "Large Coulomb Blockade Oscillations at Room Temperature in Ultra-Narrow Wire Channel MOSFETs Formed by Slight Oxidation Process", IEEE Transactions on Nanotechnology, Vol. 2, No. 4, pp. 241 - 245, December, 2003
[51]H. Im, T. Inukai, H. Gomyo, T. Hiramoto, and T. Sakurai, "VTCMOS characteristics and its optimum conditions predicted by a compact analytical model", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 755 - 761, October, 2003.
[50]Toshiro Hiramoto, H. Majima, and Masumi Saitoh, "Quantum effects and single-electron charging effects in nano-scale silicon MOSFETs at room temperature", Materials Science and Engineering B, Vol. 101, Issues 1-3, pp. 24 - 27, August, 2003.
[49]M. Saitoh, H. Majima, and T. Hiramoto, "Tunneling Barrier Structure in Room-Temperature Operating Silicon Single-Electron and Single-Hole Transistors ", Japanese Journal of Applied Physics, Vol. 42, Part 1, No. 4B, pp. 2426 - 2428, April, 2003.
[48]Q. Liu, T. Sakurai, and T. Hiramoto, "Optimum Device Consideration for Standby Power Reduction Scheme Using Drain Induced Barrier Lowering (DIBL)", Japanese Journal of Applied Physics, Vol. 42, Part 1, No. 4B, pp. 2171 - 2175, April, 2003.
[47]T. Nagumo and T. Hiramoto, "Current Drive Improvement by Enhanced Body Effect Factor Due to Finite Inversion Layer Thickness in Variable Threshold Voltage CMOS", Japanese Journal of Applied Physics, Vol. 42, Part 1, No. 4B, pp. 1988 - 1992, April, 2003.
[46]T. Hiramoto, T. Saito, and T. Nagumo, "Future Electron Devices and SOI Technology - Semi-Planar SOI MOSFETs with Sufficient Body Effect", Japanese Journal of Applied Physics, Vol. 42, Part 1, No. 4B, pp. 1975 - 1978, April, 2003.
[45]M. Saitoh, E. Nagata, and T. Hiramoto, "Large memory window and long charge retention time in ultra-narrow channel silicon floating-dot memory", Applied Physics Letters, Vol. 82, No. 11, pp. 1787 - 1789, March, 2003.
[44]Masumi Saitoh, Tasuku Murakami, and Toshiro Hiramoto, "Effects of Oxidation Process on the Tunneling Barrier Structures in Room-Temperature Operating Silicon Single-Electron Transistors", IEEE Transactions on Nanotechnology, Vol. 1, No. 4, pp. 214 - 218, December, 2002.
[43]T. Saito, T. Saraya, T. Inukai, H. Majima, T. Nagumo, and T. Hiramoto, "Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs", IEICE Transactions on Electronics, Vol. E85-C, No. 5, pp. 1073 - 1078, May, 2002.
[42]M. Saitoh and T. Hiramoto, "Current Staircase Characteristics in Silicon Single Electron Transistors with Low Parasitic Resistance", Journal of Applied Physics, Vol. 91, No. 10, pp. 6725 - 6728, May, 2002.
[41]T. Inukai, H. Im, and T. Hiramoto, "Origin of Critical Substrate Bias in Variable Threshold Voltage Complementary MOS (VTCMOS)", Japanese Journal of Applied Physics, Vol. 41, Part 1, No. 4B, pp. 2312 - 2315, April, 2002.
[40]Masumi Saitoh, Toshiki Saito, Takashi Inukai, and Toshiro Hiramoto, "Transport spectroscopy of the ultra small silicon quantum dot in a single-electron transistor", Applied Physics Letters, Vol. 79, No. 13, pp. 2025 - 2027, September, 2001.
[39]Masumi Saitoh and Toshiro Hiramoto, "Effects of Discrete Quantum Levels on Electron Transport in Silicon Single-Electron Transistors with an Ultra-Small Quantum Dot", IEICE Transactions of Electronics, Vol. E84-C, No. 8, pp. 1074 - 1076, August, 2001.
[38]Makoto Takamiya and Toshiro Hiramoto, "High Drive-Current Electrically Induced Body Dynamic Threshold SOI MOSFET (EIB-DTMOS) with Large Body Effect and Low Threshold Voltage", IEEE Transactions on Electron Devices, Vol. 48, No. 8, pp. 1633 - 1640, August, 2001.
[37]Toshiro Hiramoto, Makoto Takamiya, Hiroshi Koura, Takashi Inukai, Hiroyuki Gomyo, Hiroshi Kawaguchi, and Takayasu Sakurai, "Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)", Japanese Journal of Applied Physics, Vol. 40, Part 1, No. 4B, pp. 2854 - 2858, April, 2001.
[36]H. N. Wang, N. Takahashi, H. Majima, T. Inukai, and T. Hiramoto, "Effects of Dot Size and its Distribution on Electron Number Control in Metal-Oxide-Semiconductor-Field-Effect-Transistor Memories Based on Silicon Nanocrystal Floating Dots", Japanese Journal of Applied Physics, Vol. 40, Part 1, No. 3B, pp. 2038 - 2040, March, 2001.
[35]M. Saitoh, N. Takahashi, H. Ishikuro, and T. Hiramoto, "Large Electron Addition Energy above 250 meV in the Silicon Quantum Dot in a Single Electron Transistor", Japanese Journal of Applied Physics, Vol. 40, Part 1, No. 3B, pp. 2010 - 2012, March, 2001.
[34]Y. Shi, X. L. Yuan, J. Wu, H. M. Bu, H. G. Yang, P. Han, Y. D. Zheng, and T. Hiramoto, "Dynamics of Tunneling into Charge-Tunable Si Quantum Dots", Superlattices and Microstructures, Vol. 28, No. 5/6, pp. 387 - 392, November/December, 2000.
[33]Yuri Yasuda, Makoto Takamiya, and Toshiro Hiramoto, "Threshold Voltage Fluctuations Induced by Statistical "Position" and "Number" Impurity Fluctuations in Bulk MOSFETs", Superlattices and Microstructures, Vol. 28, No. 5/6, pp. 357 - 361, November/December, 2000.
[32]Y. Yasuda, M. Takamiya, and T. Hiramoto, "Separation of Effects of Statistical Impurity Number Fluctuations and Position Distribution on Vth Fluctuations in Scaled MOSFETs", IEEE Transactions on Electron Devices, Vol. 47, No. 10, pp. 1838 - 1842, October, 2000.
[31]T. Hiramoto (Invited), "To fill the gap between Si-ULSI and nanodevices", International Journal of High Speed Electronics and Systems (IJHSES), Vol. 10, No. 1, pp. 197 - 203, 2000.
[30]X. L. Yuan, Y. Shi, S. L. Gu, J. M. Zhu, Y. D. Zheng, K. Saito, H. Ishikuro, and T. Hiramoto, "Effects of interface traps in silicon-quantum-dots-based memory structures", Physica E, Vol. 8, No. 2, pp. 189-193, August, 2000.
[29]H. Majima, H. Ishikuro, and T. Hiramoto, "Experimental Evidence for Quantum Mechanical Narrow Channel Effect in Ultra-Narrow MOSFETs", IEEE Electron Devices Letters, Vol. 21, No. 8, pp. 396 - 398, August, 2000.
[28]A. Garnier, T. Bourouina, H. Fujita, T. Hiramoto, E. Orsier, J-C. Peuzin, "Magnetic actuation of bending and torsional vibrations for 2D-optical scanner application," Sensors and Actuators A, Physical, Vol. 84, No. 1-2, pp. 156 - 160, August, 2000.
[27]H. M. Bu, Y. Shi, X. L. Yuan, Y. D. Zheng, S. H. Gu, H. Majima, H. Ishikuro, and T. Hiramoto, "Impact of the Device Scaling on the Low-Frequency Noise in n-MOSFETs", Applied Physics A, Vol. A71, No. 2, pp. 133 - 136, June, 2000.
[26]H. M. Bu, Y. Shi, X. L. Yuan, J. Wu, S. L. Gu, and Y. D. Zheng, H. Majima, H. Ishikuro, and T. Hiramoto, "Random telegraph signals and low-frequency noise in n-metal-oxide-semiconductor field-effect transistors with ultranarrow channels," Applied Physics Letters, Vol. 76, No. 22, pp. 3259 - 3261, May, 2000.
[25]H. Koura, M. Takamiya, and T. Hiramoto, "Optimum Conditions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs" Japanese Journal of Applied Physics, Vol. 39, No. 4B, pp. 2312 - 2317, April, 2000.
[24]T. Inukai and T. Hiramoto, "Suppression of Stand-by Tunnel Current in Ultra-thin Gate Oxide MOSFETs by Dual Oxide Thickness MTCMOS (DOT-MTCMOS)", Japanese Journal of Applied Physics, Vol. 39, No. 4B, pp. 2287 - 2290, April, 2000.
[23]Toshiro Hiramoto and Makoto Takamiya (Invited), "Low Power and Low Voltage MOSFETs with Variable Threshold Voltage Controlled by Back-Bias", IEICE Transactions on Electronics, Vol. E83-C, No. 2, pp. 161 - 169, February, 2000.
[22]Nobuyoshi Takahashi, Hiroki Ishikuro, and Toshiro Hiramoto, "Control of Coulomb blockade oscillations in silicon single electron transistor using silicon nano-crystal floating gates", Applied Physics Letters, Vol. 76, No. 2, pp. 209 - 211, January, 2000.
[21]Eiji Nagata, Nobuyoshi Takahashi, Yuri Yasuda, Takashi Inukai, Hiroki Ishikuro, and Toshiro Hiramoto, "Characteristic Distributions of Narrow Channel Metal-Oxide-Semiconductor Field-Effect-Transistor Memories with Silicon Nanocrystal Floating Gates", Japanese Journal of Applied Physics, Vol. 38, No. 12B, pp. 7230 - 7232, December, 1999.
[20]Toshiro Hiramoto, H. Ishikuro, and H. Majima (Invited), "Highly Integrated Single Electron Devices and Giga-bit Lithography", Journal of Photopolymer Science and Technology, Vol. 12, No. 3, pp. 417 - 422, June, 1999.
[19]Toshiro Hiramoto and Hiroki Ishikuro, "Coulomb Blockade in VLSI-Compatible Multiple-Dot and Single-Dot MOSFETs", International Journal of Electronics, Vol. 86, No. 5, pp. 591 - 603, May, 1999.
[18]Yi Shi, Kenichi Saito, Hiroki Ishikuro, and Toshiro Hiramoto, "Characteristics of Narrow Channel MOSFET Memory Based on Silicon Nanocrystals", Japanese Journal of Applied Physics, Vol. 38, No. 4B, pp. 2453 - 2456, April, 1999.
[17]Makoto Takamiya, Takuya Saraya, Tran Ngoc Duyet, Yuri Yasuda, and Toshiro Hiramoto, "High Performance Accumulated Back-Interface Dynamic Threshold SOI MOSFET's (AB-DTMOS) with Large Body Effect at Low Supply Voltage", Japanese Journal of Applied Physics, Vol. 38, No. 4B, pp. 2483 - 2486, April, 1999.
[16]Tran Ngoc Duyet, Hiroki Ishikuro, Yi Shi, Takuya Saraya, Makoto Takamiya, and Toshiro Hiramoto, "Measurement of Energetic and Lateral Distribution of Interface State Density in FD SOI MOSFETs", Japanese Journal of Applied Physics, Vol. 38, No. 4B, pp. 2496 - 2500, April, 1999.
[15]H. Ishikuro and T. Hiramoto, "On the origin of tunneling barriers in silicon single electron and single hole transistors", Applied Physics Letters, Vol. 74, No. 8, pp. 1126 - 1128, February, 1999.
[14]Toshiro Hiramoto and Hiroki Ishikuro, "Quantum Energy and Charging Energy in Point Contact MOSFETs acting as Single Electron Transistors", Superlattices and Microstructures, Vol. 24, No. 1/2, pp. 263 - 267, 1999.
[13]Yi Shi, Kenichi Saito, Hiroki Ishikuro, and Toshiro Hiramoto, "Effects of Interface Traps on Charge Retention Characteristics in Silicon-Quantum-Dot-Based Metal-Oxide-Semiconductor Diodes", Japanese Journal of Applied Physics, Vol. 38, Part 1, No. 1B, pp. 425 - 428, January, 1999.
[12]Hiroki Ishikuro and Toshiro Hiramoto, "Fabrication of Nano-Scale Point Contact Metal-Oxide-Semiconductor Field-Effect-Transistors Using Micrometer-Scale Design Rule", Japanese Journal of Applied Physics, Vol. 38, Part 1, No. 1B, pp. 396 - 398, January, 1999.
[11]Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, "Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals", Journal of Applied Physics, Vol. 84, No. 4, pp. 2358 - 2360, August, 1998.
[10]T. Mukaiyama, K. Saito, H. Ishikuro, M. Takamiya, T. Saraya, and T. Hiramoto, "Fabrication of Gate-All Around MOSFET by Silicon Anisotropic Etching Technique", Solid State Electronics, Vol. 42, No. 7-8, pp. 1623 - 1626, July - August, 1998.
[9]H. Ishikuro and T. Hiramoto, "Hopping Transport in Multiple-Dot Silicon Single Electron MOSFET, Solid State Electronics", Vol. 42, No. 7-8, pp. 1425 - 1428, July - August, 1998.
[8]N. Duyet, H. Ishikuro, M. Takamiya, T. Saraya, and T. Hiramoto, "Suppression of Geometric Component of Charge Pumping Current in Thin Film SOI MOSFET", Japanese Journal of Applied Physics, Part 2, Vol. 37, No. 7B, pp. L855 - L858, July, 1998.
[7]T. Saraya, M. Takamiya, T.N. Duyet, and T. Hiramoto, "New Measurement Technique of Sub-Bandgap Impact Ionization Current by Transient Characteristics of Partially Depleted SOI MOSFETs", Japanese Journal of Applied Physics, Vol. 37, Part 1, No. 3B, pp. 1271 - 1273, March, 1998.
[6]Hiroki Ishikuro and Toshiro Hiramoto, "Quantum mechanical effects in the silicon quantum dot in a single-electron-transistor", Applied Physics Letters, Vol. 71, No. 25, pp. 3691 - 3693, December, 1997.
[5]T. Hiramoto, H. Ishikuro, T. Fujii, G. Hashiguchi, and T. Ikoma, "Room Temperature Coulomb Blockade and Low Temperature Hopping Transport in a Multiple-Dot-Channel MOSFET", Japanese Journal of Applied Physics, Vol. 36, No. 6B, pp. 4139 - 4142, June, 1997.
[4]T. Hiramoto, H. Ishikuro, K. Saito, T. Fujii, T. Saraya, G. Hashiguchi, and T. Ikoma, "Fabirication of Si Nano-Structures for Single Electron Device Applications by Anisotropic Etching", Japanese Journal of Applied Physics, Vol. 35, No. 12B, pp. 6664 - 6667, December, 1996.
[3]H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, T. Hiramoto, and T. Ikoma, "Coulomb Blockade Oscillations at Room Temperature in a Si Quantum Wire Metal-Oxide-Semiconductor Field-Effect-Transistor Fabricated by Anisotropic Etching on a Silicon-on-Insulator Substrate", Applied Physics Letters, Vol. 68, No. 25, pp. 3585 - 3587, June, 1996.
[2]T. Hiramoto, H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, and T. Ikoma, "Characterization of Precisely Width-Controlled Si Quantum Wires Fabricated on SOI Substrates", Physics B, Vol. 227, pp. 95 - 97, 1996.
[1]H. Ishikuro, T. Saraya, T. Hiramoto, and T. Ikoma, "Extremely Large Amplitude Random Telegraph Signals in a Very Narrow Split-Gate MOSFET at Low Temperatures", Japanese Journal of Applied Physics, Vol. 35, No. 2B, pp. 858 - 860, February, 1996.

日本語論文誌

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[13]平本俊郎,竹内潔,西田彰男,「MOSトランジスタのスケーリングに伴う特性ばらつき」,電子情報通信学会会誌,Vol. 92, No. 6, pp. 416 - 426, 2009年6月.
[12]平本俊郎,竹内潔,西田彰男,「増大する微細MOSトランジスタの特性 ばらつき:現状と対策」,電気学会論文誌C,Vol. 128, No. 6, pp. 820 - 824, 2008年6月.
[11]平本俊郎,「新構造MOSトランジスタ技術」,電子情報通信学会誌「サブ100nm時 代のシステムLSIとビジネスモデル小特集」,Vol. 89,No. 2,pp. 123 - 129,2006 年2月.
[10]平本俊郎,「「ナノテク」時代迎えた半導体 高度情報化社会の成否がかかる」,Science and Technology Journal, Vol. 13, No, 11, pp. 18 - 19, 2004年11月.
[9]平本俊郎,「極限CMOS開発の現状と将来展望」,機能材料,Vol. 24,No. 9,pp. 5 - 13,2004年9月.
[8]平本俊郎,「ナノスケール狭チャネルMOSFETにおける量子効果」,応用物理,Vol. 72, No. 9, pp. 1167 - 1170, 2003年9月.
[7]平本俊郎,「極薄膜狭チャネルSOI MOSFETにおける量子効果」,超精密,Vol. 12, pp. 81 - 85, 2002年12月.
[6]平本俊郎,「シリコンナノドットを用いたメモリデバイス」,電子情報通信学会誌,Vol. 85, No. 11, pp. 794 - 799, 2002年11月.
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[4]平本俊郎,「電子1個で動くトランジスタ」,電気学会誌,Vol. 120,No. 8/9,pp. 518 - 521,2000 年 8 月.
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[1]田部道晴,小田俊理,平本俊郎,中里和郎,雨宮好仁, 「単電子デバイス・回路の研究状況と今後の展望」, 応用物理,Vol. 66,No. 2, pp. 99 - 108, 1997 年 2 月.