International Meetings and Conferences

Index

 IEDM
 Symposium on VLSI Technology
 CICC
 International SOI Conference
 SSDM
 Silicon Nanoelectronics Workshop
 ICMTS
 ISLPED
 IEEE-NANO
 NanoMES
 SISPAD
 ICPS
 DRC
 MNC
 ISDRS
 QDS
 QFD
 ICICDT

25 Papers in IEDM

[25]Masaharu Kobayashi, Nozomu Ueyama, Kyungmin Jang, and Toshiro Hiramoto, “Experimental Study on Polarization-Limited Operation Speed of Negative Capacitance FET with Ferroelectric HfO2”, IEEE International Electron Devices Meeting (IEDM), Hilton San Francisco Union Square, San Francisco, CA, USA, pp. 314 - 317, December 6, 2016.
[24]K. Kakushima, T. Hoshii, K. Tsutsui, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, and H. Iwai, IEEE International Electron Devices Meeting (IEDM), Hilton San Francisco Union Square, San Francisco, CA, USA, pp. 268 - 271, December 6, 2016.
[23]M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, M. Kobayashi, E. Higurashi, H. Toshiyoshi, and T. Hiramoto, "Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers", San Francisco, CA, USA, December 15, 2014.
[22]Tomoko Mizutani, Anil Kumar, and Toshiro Hiramoto, "Analysis of Transistor Characteristics in Distribution Tails beyond ±5.4σ of 11 Billion Transistors", IEEE International Electron Devices Meeting (IEDM), Washington, D.C., USA, pp. 826 - 829, December 11, 2013.
[21]H. Makiyama, Y. Yamamoto, H. Shinohara, T. Iwamatsu, H. Oda, N. Sugii, K. Ishibashi, T. Mizutani, T. Hiramoto, and Y. Yamaguchi, "Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation", IEEE International Electron Devices Meeting (IEDM), Washington, D.C., USA, pp. 822 - 825, December 11, 2013.
[20]Tomoko Mizutani, Anil Kumar, and Toshiro Hiramoto, "Measuring Threshold Voltage Variability of 10G Transistors", International Electron Devices Meeting (IEDM), Washington, D.C., USA, pp. 563 E566, December 7, 2011.
[19]X. Song, M. Suzuki, T. Saraya, A. Nishida, T. Tsunomura, S. Kamohara, K. Takeuchi, S. Inaba, T. Mogami, and T. Hiramoto, "Impact of DIBL Variability on SRAM Static Noise Margin Analyzed by DMA SRAM TEG", International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 62 - 65, December 6, 2010.
[18]Ken Shimizu, Takuya Saraya, and Toshiro Hiramoto, "Physical Understandings of Si (110) Hole Mobility in Ultra-Thin Body pFETs by <110> and <111> Uniaxial Compressive Strain", International Electron Devices Meeting (IEDM), Baltimore, MD, USA, pp. 473 - 476, December 8, 2009.
[17]YeonJoo Jeong, Jiezhi Chen, Takuya Saraya, and Toshiro Hiramoto, "Uniaxial Strain Effects on Silicon Nanowire pMOSFET and Single-Hole Transistor at Room Temperature", IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 761 - 764, December 17, 2008.
[16]Jiezhi Chen, Takuya Saraya, and Toshiro Hiramoto, "Electron Mobility in Multiple Silicon Nanowires GAA nMOSFETs on (110) and (100) SOI at Room and Low Temperature", IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 757 - 760, December 17, 2008.
[15]Ken Shimizu, Takuya Saraya and Toshiro Hiramoto, "Experimental Investigation on the Origin of Direction Dependence of Si (110) Hole Mobility Utilizing Ultra-Thin Body pMOSFETs", IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 67 - 70, December 15, 2008.
[14]Ken Shimizu and Toshiro Hiramoto, "Mobility Enhancement in Uniaxially Strained (110) oriented Ultra-Thin Body Single- and Double-Gate MOSFETs with SOI Thickness of less than 4 nm", International Electron Devices Meeting (IEDM), Washington Hilton, Washington D. C., USA, pp. 715 - 718, December 12, 2007.
[13]K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto, "Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies", International Electron Devices Meeting (IEDM), Washington Hilton, Washington D. C., USA, pp. 467 - 470, December 11, 2007.
[12]Masaharu Kobayashi and Toshiro Hiramoto, "Experimental Study on Quantum Structure of Silicon Nano Wire and Its Impact on Nano Wire MOSFET and Single-Electron Transistor", IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 1007 - 1009, December, 2006.
[11]Tetsu Ohtou, Takuya Saraya, Kimiaki Shimokawa, Yasuhiro Doumae, Yoshiki Nagatomo, Jiro Ida and Toshiro Hiramoto, "Experimental Demonstrations of Superior Characteristics of Variable Body-Factor (ƒÁ) Fully-Depleted SOI MOSFETs with Extremely Thin BOX of 10nm", IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. pp. 877 - 880 December, 2006.
[10]Gen Tsutsui, Masumi Saitoh, Takuya Saraya, Toshiharu Nagumo, and Toshiro Hiramoto, "Mobility Enhancement due to Volume Inversion in (110)-oriented Ultra-thin Body Double-gate nMOSFETs with Body Thickness less than 5 nm", International Electron Devices Meeting (IEDM), Washington D.C., USA, pp. 747 - 750, December, 2005.
[9]Masumi Saitoh, Hidehiro Harata, and Toshiro Hiramoto, "Room-Temperature Demonstration of Integrated Silicon Single-Electron Transistor Circuits for Current Switching and Analog Pattern Matching", IEEE Electron Devices Meeting (IEDM), San Francisco, USA, pp. 187 - 190, December, 2004. This paper received the 2004 Roger A. Haken Best Student Paper Award.
[8]Il-Gweon Kim, Kosuke Yanagidaira, and Toshiro Hiramoto, "Integration of Fluorinated Nano-Crystal Memory Cells with 4.6F2 Size by Landing Plug Polysilicon Contact and Direct-Tungsten Bitline", 2003 International Electron Devices Meeting (IEDM), Washington DC, USA, pp. 605 - 608, December, 2003.
[7]Masumi Saitoh and Toshiro Hiramoto, "Room-Temperature Operation of Highly Functional Single-Electron Transistor Logic Based on Quantum Mechanical Effect in Ultra-Small Silicon Dot", 2003 International Electron Devices Meeting (IEDM), Washington DC, USA, pp. 753 - 756, December, 2003.
[6]M. Saitoh, E. Nagata, and T. Hiramoto, "Effects of ultra-narrow channel on characteristics of MOSFET memory with silicon nanocrystal floating gates", 2002 IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, pp. 181 - 184, December, 2002.
[5]H. Majima, Y. Saito, and T. Hiramoto, "Impact of Quantum Mechanical Effects on Design of Nano-scale Narrow Channel n- and p-type MOSFETs", 2001 IEEE International Electron Devices Meeting (IEDM), Washington D.C., USA, pp. 733 - 736, December, 2001. This paper received the 2001 Roger A. Haken Best Student Paper Award.
[4]H. Majima, H. Ishikuro, and T. Hiramoto, "Threshold Voltage Increase by Quantum Mechanical Narrow Channel Effect in Ultra-Narrow MOSFETs", 1999 IEEE International Electron Devices Meeting (IEDM), Washington D.C., USA, pp. 379 - 382, December, 1999.
[3]N. Takahashi, H. Ishikuro, and T. Hiramoto, "A Directional Current Switch Using Silicon Single Electron Transistors Controlled by Charge Injection into Silicon Nano-Crystal Floating Dots", 1999 IEEE International Electron Devices Meeting (IEDM), Washington D.C., USA, pp. 371 - 374, December, 1999.
[2]Makoto Takamiya and Toshiro Hiramoto, "High Performance Electrically Induced Body Dynamic Threshold SOI MOSFET (EIB-DTMOS) with Large Body Effect and Low Threshold Voltage", 1998 IEEE International Electron Devices Meeting, pp. 423 - 426, San Francisco, USA, December, 1998.
[1]Hiroki Ishikuro and Toshiro Hiramoto, "Influence of Quantum Confinement Effects on Single Electron and Single Hole Transistors", 1998 IEEE International Electron Devices Meeting, pp. 119 - 123, San Francisco, USA, December, 1998.

19 Papers in Symposium on VLSI Technology

[21]Masaharu Kobayashi, Nozomu Ueyama and Toshiro Hiramoto, “A Nonvolatile SRAM Integrated with Ferroelectric HfO2 Capacitor for Normally-Off and Ultralow Power IoT Application”, Symposium on VLSI Technology, Rihga Royal Hotel Kyoto, Kyoto, pp. T156 – T157, June 7, 2017.
[20]Hao Qiu, Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Jiezhi Chen, Masaharu Kobayashi, and Toshiro Hiramoto, “Statistical Analyses of Random Telegraph Noise Amplitude in Ultra-Narrow (Deep Sub-10nm) Silicon Nanowire Transistors”, Symposium on VLSI Technology, Rihga Royal Hotel Kyoto, Kyoto, pp. T50 – T51, June 6, 2017.
[19]Masaharu Kobayashi and Toshiro Hiramoto, “Device Design Guideline for Steep Slope Ferroelectric FET Using Negative Capacitance in Sub-0.2V Operation: Operation Speed, Material Requirement and Energy Efficiency”, VLSI Symposium on Technology, Rihga Royal Hotel Kyoto, Kyoto, pp. T212 - T213, June 18, 2015.
[18]Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, Y. Yamaguchi, T. Mizutani, M. Kobayashi and T. Hiramoto, “Novel Single p+Poly-Si/Hf/SiON Gate Stack Technology on Silicon-on-Thin-Buried-Oxide (SOTB) for Ultra-Low Leakage Applications”, VLSI Symposium on Technology, Rihga Royal Hotel Kyoto, Kyoto, pp. T170 - T171, June 17, 2015.
[17]Hao Qiu, Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “Impact of Random Telegraph Noise on Write Stability in Silicon-on-Thin-BOX (SOTB) SRAM Cells at Low Supply Voltage in Sub-0.4V Regime”, VLSI Symposium on Technology, Rihga Royal Hotel Kyoto, Kyoto, pp. T38 - T39, June 16, 2015.
[16]Akitsugu Ueda, Seung-Min Jung, Tomoko Mizutani, Anil Kumar, Takuya Saraya, and Toshiro Hiramoto, "Ultra-Low Voltage (0.1V) Operation of Vth Self-Adjusting MOSFET and SRAM Cell", VLSI Symposium on Technology, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 198 - 199, June 12, 2014.
[15]Shiro Kamohara, Nobuyuki Sugii, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Masaru Kadoshima, Keiichi Maekawa, Hitoshi Mitani, Yasushi Yamagata, Hidekazu Oda, Yasuo Yamaguchi, Koichiro Ishibashi, Hideharu Amano, Kimiyoshi Usami, Kazutoshi Kobayashi, Tomoko Mizutani, Toshiro Hiramoto (Invited), "Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era", VLSI Symposium on Technology, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 190 - 191, June 12, 2014.
[14]Y. Yamamoto, H. Makiyama, H. Shinohara, T. Iwamatsu, H. Oda, S. Kamohara, N. Sugii, Y. Yamaguchi, T. Mizutani and T. Hiramoto, "Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias", VLSI Symposium on Technology, pp. T212 - T213, June 13, 2013.
[13]Y. Yamamoto, H. Makiyama, T. Tsunomura, T. Iwamatsu, H. Oda, N. Sugii, Y. Yamaguchi, T. Mizutani and T. Hiramoto, "Poly/High-k/SiON Gate Stack and Novel Profile Engineering Dedicated for Ultralow-Voltage Silicon-on-Thin-BOX (SOTB) CMOS Operation", Symposium on VLSI Technology, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 109 - 110, June 11, 2012.
[12]K. Takeuchi, A. Nishida, S. Kamohara, T. Hiramoto and T. Mogami, "Proposal of a Model for Increased NFET Random Fluctuations", Symposium on VLSI Technology, Rihga Royal Hotel Kyoto, pp. 192 - 193, June 16, 2011.
[11]T. Tsunomura, J. Nishimura, A. Kumar, A. Nishida, S. Inaba, K. Takeuchi, T. Hiramoto and T. Mogami, "Suppression of VT Variability Degradation Induced by NBTI with RDF Control", Symposium on VLSI Technology, Rihga Royal Hotel Kyoto, pp. 150 - 151, June 15, 2011.
[10]M. Suzuki, T. Saraya, K. Shimizu, A. Nishida, S. Kamohara, K. Takeuchi, S. Miyano, T. Sakurai, and T. Hiramoto, "Direct Measurements, Analysis, and Post-Fabrication Improvement of Noise Margins in SRAM Cells Utilizing DMA SRAM TEG", VLSI Symposium on Technology, Hilton Hawaiian Village, HI. USA, pp. 191 - 192, June 17, 2010.
[9]Jiezhi Chen, Takuya Saraya, and Toshiro Hiramoto, "Mobility Enhancement over Universal Mobility in (100) Silicon Nanowire Gate-All-Around MOSFETs with Width and Height of Less Than 10nm Range", VLSI Symposium on Technology, Hilton Hawaiian Village, HI. USA, pp. 175 - 176, June 17, 2010.
[8]T. Tsunomura, A. Kumar, T. Mizutani, C. Lee, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, T. Mogami, "Analysis and Prospect of Local Variability of Drain Current in Scaled MOSFETs by a New Decomposition Method", VLSI Symposium on Technology, Hilton Hawaiian Village, HI. USA, pp. 97 - 98, June 16, 2010.
[7]Makoto Suzuki, Takuya Saraya, Ken Shimizu, Takayasu Sakurai, and Toshiro Hiramoto, "Post-Fabrication Self-Convergence Scheme for Suppressing Variability in SRAM Cells and Logic Transistors", Symposium on VLSI Technology, Rihga Royal Hotel Kyoto, pp. 148 - 149, June 16, 2009.
[6]A. T. Putra, T. Tsunomura, A. Nishida, S. Kamohara, K. Takeuchi, S. Inaba, K. Terada, and T. Hiramoto, "A New Methodology for Evaluating VT Variability Considering Dopant Depth Profile", Symposium on VLSI Technology, Rihga Royal Hotel Kyoto, pp. 116 - 117, June 16, 2009.
[5]T. Tsunomura, A. Nishida, F. Yano, A. T. Putra, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Mama, T. Hiramoto, T. Mogami, "Analysis of Extra VT Variability Sources in NMOS Using Takeuchi Plot", Symposium on VLSI Technology, Rihga Royal Hotel Kyoto, pp. 110 - 111, June 16, 2009.
[4](259) Jiezhi Chen, Takuya Saraya, and Toshiro Hiramoto, "High Hole Mobility in Multiple Silicon Nanowire Gate-All-Around pMOSFETs on (110) SOI", Symposium on VLSI Technology, Rihga Royal Hotel Kyoto, pp. 90 - 91, June 16, 2009.
[3]T. Tsunomura, A. Nishida, F. Yano, A. T. Putra, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami, "Analyses of 5ƒÐ Vth Fluctuation in 65nm-MOSFETs Using Takeuchi Plot", Symposium on VLSI Technology, pp. 156 - 157, Hilton Hawaiian Village, HI, USA, June 19, 2008.
[2]Jiezhi Chen, Takuya Saraya, Kousuke Miyaji, Ken Shimizu, and Toshiro Hiramoto, "Experimental Study of Mobility in [110]- and [100]-Directed Multiple Silicon Nanowire GAA MOSFETs on (100) SOI", Symposium on VLSI Technology, pp. 32 - 33, Hilton Hawaiian Village, HI, USA, June 17, 2008.
[1]Gen Tsutsui, Masumi Saitoh, and Toshiro Hiramoto, "Superior Mobility Characteristics in (110)-Oriented Ultra Thin Body pMOSFETs with SOI Thickness less than 6 nm", Symposium on VLSI Technology, Rihga Royal Hotel Kyoto, pp. 76 - 77, June, 2005.

Two Papers in CICC

[2]Toshiro Hiramoto, Anil Kumar, Tomoko Mizutani, Jun Nishimura, and Takuya Saraya (Invited), "Statistical Advantages of Intrinsic Channel Fully Depleted SOI MOSFETs over Bulk MOSFETs", Custom Integrated Circuits Conference (CICC), Doubletree Hotel, San Jose, CA, USA, paper 5-2, September 19, 2011.
[1]T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, T. Sakurai, "Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration", Custom Integrated Circuits Conference, Florida, USA, pp. 409 - 412, May, 2000.

14 Papers in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (Formerly, IEEE International SOI Conference)

[14]Seung-Min Jung, Takuya Saraya, Kiyoshi Takeuchi, Masaharu Kobayashi and Toshiro Hiramoto, “Vth Self-Adjusting Tri-Gate Nanowire MOSFET for Stability Improvement of SRAM Cell Operating at 0.1 V”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), The DoubleTree by Hilton Sonoma Wine Country, Rohnert Park, CA, USA, Paper 11.4, October 6, 2015.
[13]Masahide Goto, Kei Hagiwara, Yuki Honda, Masakazu Nanba, Hiroshi Ohtake, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “128 × 96 Pixel-Parallel Three-Dimensional Integrated CMOS Image Sensors with 16-bit A/D Converters by Direct Bonding with Embedded Au Electrodes”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), The DoubleTree by Hilton Sonoma Wine Country, Rohnert Park, CA, USA, Paper 7c.3, October 5, 2015.
[12]M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, E. Higurashi, H. Toshiyoshi, and T. Hiramoto, "Three-Dimensional Integrated Circuits with NFET and PFET on Separate Layers Fabricated by Low Temperature Au/SiO2 Hybrid Bonding", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Hyatt Regency Monterey Hotel and Spa, Monterey, CA, USA, Paper 11.2, October 10, 2013.
[11]N. Sugii, T. Iwamatsu, Y. Yamamoto, H. Makiyama, H. Shinohara, H. Oda, S. Kamohara, Y. Yamaguchi, K. Ishibashi, T. Mizutani, and T. Hiramoto (Invited), "Vmin=0.4 V LSIs are the real with Silicon-on-Thin-Buried-Oxide (SOTB) -How is the application with "Perpetuum-Mobile" micro-controller with SOTB?", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Hyatt Regency Monterey Hotel and Spa, Monterey, CA, USA, Paper 8b.1, October 10, 2013.
[10]T. Hiramoto, T. Mizutani, A. Kumar, A. Nishida, T. Tsunomura, S. Inaba, K. Takeuchi, S. Kamohara, and T. Mogami, "Suppression of DIBL and Current-Onset Voltage Variability in Intrinsic Channel Fully Depleted SOI MOSFETs", IEEE International SOI Conference, San Diego, CA, USA, pp. 170 - 171, October 14, 2010.
[9]Ken Shimizu, Takuya Saraya and Toshiro Hiramoto, "Superior <110>-Directed Mobility to <100>-Directed Mobility in Ultrathin Body (110) nMOSFETs", IEEE International SOI Conference, Crowne Plaza Hotel, Foster City, CA, USA, No. 11.4, October 9, 2009.
[8]Ken Shimizu and Toshiro Hiramoto, "Suppression of Electron Mobility Degradation in (100)-Oriented Double-Gate Ultra-Thin Body nMOSFETs with SOI Thickness of Less Than 2 nm", IEEE International SOI Conference, Miramonte Resort & Spa, Indian Wells, CA, USA, pp. 145 - 146, October 4, 2007.
[7]Ken Shimizu, Gen Tsutsui, and Toshiro Hiramoto, "Experimental Study on Mobility Universality in (100) Ultra Thin Body nMOSFET with SOI Thickness of 5nm", 2006 IEEE International SOI Conference, Niagara Falls, NY, USA, pp. 159 - 160, October, 2006.
[6]Tetsu Ohtou, Kouki Yokoyama, Toshiharu Nagumo and Toshiro Hiramoto, "Vth Control of tpd-Degradation-Free FD SOI MOSFET with Extremely Thin BOX Using Variable Body-Factor Scheme", IEEE International SOI Conference, Hyatt Regency Waikiki Resort & Spa, Honolulu, Hawaii, USA, pp. 101 - 103, October, 2005.
[5]Anil Kumar, Toshiharu Nagumo, Gen Tsutsui and Toshiro Hiramoto "Degradation of Body Factor () of Single Gate Fully Depleted SOI MOSFETs Due to Short Channel Effects", IEEE International SOI Conference, Francis Marion Hotel, Charleston, SC, USA, pp. 58 - 59, October, 2004.
[4]T. Hiramoto (Invited), "Nano-Scale Silicon MOSFET: Towards Non-Traditional and Quantum Devices", 2001 IEEE International SOI Conference, Sheraton Tamarron Resort, Durango, CO, USA, pp. 8 - 10, October, 2001.
[3]T. Saraya and T. Hiramoto, "Mechanisms of dynamic pass leakage current in partially depleted SOI MOSFETs", 1999 IEEE International SOI Conference, Doubletree Hotel Sonoma County, CA, USA, pp. 84 - 85, October, 1999.
[2]Tran Ngoc Duyet, Hiroki Ishikuro, Makoto Takamiya, Takuya Saraya, and Toshiro Hiramoto, "Effects of Body Reverse Pulse Bias on Geometric Component of Charge Pumping Current in FD SOI MOSFETs", 1998 IEEE International SOI Conference, Stuart, Florida, USA, pp. 79 - 80, October, 1998.
[1]T. Saraya, M. Takamiya, T. N. Duyet, T. Tanaka, H. Ishikuro, T. Hiramoto, and T. Ikoma, "Floating Body Effects in 0.15 μm Partially Depleted SOI MOSFETs below 1 V", 1996 IEEE International SOI Conference, Fort Myers, Florida, USA, October, 1996.

45 Papers in SSDM

[45]Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi and Toshiro Hiramoto, “Parallel Programmable Non-volatile Memory Using Normal SRAM Cells”, International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, Ibaraki, pp. 57 - 58, September 29, 2016.
[44]Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi and Toshiro Hiramoto, “A Study on the Correlation between SRAM Power-up State and Transistor Variation”, International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, Ibaraki, pp. 55 - 56, September 29, 2016.
[43]Tomoko Mizutani, Takuya Saraya, Kiyoshi Takeuchi, Masaharu Kobayashi, and Toshiro Hiramoto, “Transistor-level Characterization of SRAM Bit Failures Induced by Random Telegraph Noise”, International Conference on Solid State Devices and Materials (SSDM), Sapporo Convention Center, Hokkaido, pp. 1010 – 1011, September 29, 2015.
[42]Hao Qiu, Tomoko Mizutani, Takuya Saraya, and Toshiro Hiramoto, "Comparison and Statistical Analysis of Four Write Stability Metrics in Bulk CMOS SRAM Cells", International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, Ibaraki, pp. 848 - 849, September 10, 2014.
[41]T. Mizutani, Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, and T. Hiramoto, "Detailed Analysis of Minimum Operation Voltage (Vmin) of Extraordinarily Unstable Cells in Fully Depleted Silicon-on-Thin-BOX (SOTB) 6T-SRAM", International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, Ibaraki, pp. 846 - 847, September 10, 2014.
[40]T. Mizutani, Y. Yamamoto, H. Makiyama, H. Shinohara, T. Iwamatsu, H. Oda, N. Sugii, and T. Hiramoto, "Comparison of Minimum Operation Voltage (Vmin) in Fully Depleted Silicon-on-Thin-BOX (SOTB) and Bulk SRAM Cells", 2013 International Conference on Solid State Devices and Materials (SSDM), Hilton Fukuoka Sea Hawk, Fukuoka, pp. 742 - 743, September 27, 2013.
[39]N. Sugii, T. Iwamatsu, Y. Yamamoto, H. Makiyama, H. Shinohara, H. Oda, S. Kamohara, Y. Yamaguchi, T. Mizutani, K. Ishibashi, and T. Hiramoto (Invited), "Ultralow-Voltage Operation SOTB Technology toward Energy Efficient Electronics", 2013 International Conference on Solid State Devices and Materials (SSDM), Hilton Fukuoka Sea Hawk, Fukuoka, pp. 736 - 737, September 27, 2013.
[38]Yuma Tanahashi, Ryota Suzuki, Takuya Saraya, and Toshiro Hiramoto, "Peak Position Control of Coulomb Oscillations in Silicon Single-Electron Transistors with Floating Gate Operating at Room Temperature", 2013 International Conference on Solid State Devices and Materials (SSDM), Hilton Fukuoka Sea Hawk, Fukuoka, pp. 778 - 779, September 26, 2013.
[37]T. Mizutani, Y. Yamamoto, H. Makiyama, T. Tsunomura, T. Iwamatsu, H. Oda, N. Sugii, and T. Hiramoto, "Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-BOX (SOTB) MOSFETs and Bulk MOSFETs", 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto International Conference Center, Kyoto, September 27, 2012.
[36]Ke Mao, Takuya Saraya, and Toshiro Hiramoto, "The impact of Side Surface Roughness on Carrier Mobility in Tri-Gate Silicon Nanowire MOSFETs", 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto International Conference Center, Kyoto, September 25, 2012.
[35]Ryota Suzuki, Motoki Nozue, Takuya Saraya, and Toshiro Hiramoto, "Integration of 1-bit CMOS Address Decoders and Single-Electron Transistors Operating at Room Temperature", 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto International Conference Center, Kyoto, pp. 943 - 944, September 25, 2012. This paper received the SSDM Young Researcher Award.
[34]Ke Mao, Takuya Saraya, and Toshiro Hiramoto, "Extraction of Carrier Mobility in Intrinsic Channel Tri-Gate Single Silicon Nanowire MOSFETs", 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto International Conference Center, Kyoto, September 25, 2012.
[33]K. Mao, T. Mizutani, A. Kumar, T. Saraya, and T. Hiramoto, "Extremely Small Within-Device Variability in Intrinsic Channel Tri-Gate Silicon Nanowire MOSFETs", 2011 International Conference on Solid State Devices and Materials (SSDM), Aichi Industry & Labor Center (WINC AICHI), no. D-6-3, September 30, 2011.
[32]T. Tsunomura, A. Kumar, T. Mizutani, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami, "High Temperature Characteristic of Radom Variability of Drain Current in Scaled FETs", International Conference on Solid-State Devices and Materials (SSDM), University of Tokyo, pp. 699 - 700, September 23, 2010.
[31]T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto and T. Mogami (Invited), "Process Condition Dependence of Random VT Variability in NFETs and PFETs", International Conference on Solid State Devices and Materials (SSDM), Sendai Kokusai Hotel, pp. 1010 - 1011, October 9, 2009.
[30]Chiho Lee, Arifin Tamsir Putra, Ken Shimizu, and Toshiro Hiramoto, "Vth Dependence of Vth Variability in Intrinsic Channel SOI MOSFETs with Ultra-Thin BOX", International Conference on Solid State Devices and Materials (SSDM), Sendai Kokusai Hotel, pp. 10 - 11, October 7, 2009.
[29]Ken Shimizu and Toshiro Hiramoto, "Mobility Degradation in (110)-Oriented Ultra-thin Body Double-Gate pMOSFETs with SOI Thickness of less than 5nm", International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, pp. 732 - 733, September 20, 2007.
[28]Kousuke Miyaji and Toshiro Hiramoto, "Room Temperature Demonstration of Variable Full Width at Half Maximum of Coulomb Oscillation in Silicon Single-Hole Transistor", International Conference on Solid State Devices and Materials (SSDM), Pacificko Yokohama, pp. 836 - 837, September, 2006.
[27]Masaharu Kobayashi, Kousuke Miyaji, and Toshiro Hiramoto, "Charge Polarity Dependence of Negative Differential Conductance in Room-Temperature Operating Silicon Single-Charge Transistors", International Conference on Solid State Devices and Materials (SSDM), Pacificko Yokohama, pp. 806 - 807, September, 2006.
[26]Doni Januar, Gen Tsutsui, Masumi Saitoh, and Toshiro Hiramoto, "Mobility Increase in High-Ns Region in (110)-Oriented UTB pMOSFET Through Surface Roughness Improvement", International Conference on Solid State Devices and Materials (SSDM), International Conference Center Kobe, Hyogo, pp. 264 - 265, September, 2005.
[25]Masaharu Kobayashi, Masumi Saitoh, and Toshiro Hiramoto, "Large Temperature Dependence of Coulomb Blockade Oscillations in Room-Temperature Operating Silicon Single-Hole Transistor", International Conference on Solid State Devices and Materials (SSDM), International Conference Center Kobe, Hyogo, pp. 164 - 165, September, 2005.
[24]Arifin Tamsir, Masumi Saitoh, Gen Tsutsui and Toshiro Hiramoto, "Modeling of Body Factor and Subthreshold Swing in Short Channel Bulk MOSFETs", International Conference on Solid State Devices and Materials (SSDM), International Conference Center Kobe, Hyogo, pp. 184 - 285, September, 2005.
[23]Kousuke Miyaji, Masumi Saitoh, and Toshiro Hiramoto, "Very Sharp Room-Temperature Negative Differential Conductance in Silicon Single-Hole Transistor with High Voltage Gain", International Conference on Solid State Devices and Materials (SSDM), International Conference Center Kobe, Hyogo, pp. 166 - 167, September, 2005.
[22]Sangsu Park, Hyunsik Im, Ilgweon Kim, and Toshiro Hiramoto, "Impact of Drain Induced Barrier Lowering on Read Scheme in Silicon Nanocrystal Memory with Two-Bit-per-Cell Operation", International Conference on Solid State Devices and Materials, Tower Hall Funabori, Tokyo, pp. 610 - 611, September, 2004.
[21]Kosuke Yanagidaira, Masumi Saitoh, and Toshiro Hiramoto, "Large Threshold Voltage Shift and Narrow Threshold Voltage Distribution in Ultra Thin Body Silicon Nanocrystal Memories", International Conference on Solid State Devices and Materials, Tower Hall Funabori, Tokyo, pp. 130 - 131, September, 2004.
[20]Kouske Miyaji, Masumi Saitoh, Toshiharu Nagumo, and Toshiro Hiramoto, "Temperature Dependence of Off-Current in Bulk and FD SOI MOSFETs," International Conference on Solid State Devices and Materials, Tower Hall Funabori, Tokyo, pp. 236 - 237, September, 2004.
[19]Fumihiko Tachibana and Toshiro Hiramoto, "Re-examination of Impact of Intrinsic Dopant Fluctuations on SRAM Static Noise Margin", International Conference on Solid State Devices and Materials, Tower Hall Funabori, Tokyo, pp. 192 - 193, September, 2004.
[18]Tetsu Ohtou, Toshiharu Nagumo, and Toshiro Hiramoto, "Short Channel Characteristics of Variable Body Factor FD SOI MOSFETs", International Conference on Solid State Devices and Materials, Tower Hall Funabori, Tokyo, pp. 502 - 503, September, 2004.
[17]Masumi Saitoh, Hidehiro Harata, and Toshiro Hiramoto, "Room Temperature Demonstration of Low-Voltage Static Memory Based on Negative Differential Conductance in Silicon Single-Hole Transistors", International Conference on Solid State Devices and Materials, Tower Hall Funabori, Tokyo, pp. 124 - 125, September, 2004. This paper received the SSDM Young Researcher Award.
[16]M. Saitoh and T. Hiramoto, "Room-Temperature Observation of Negative Differential Conductance Due to Large Quantum Level Spacing in Silicon Single-Electron Transistor", 2003 International Conference on Solid State Devices and Materials (SSDM), Keio Plaza Hotel, pp. 328 - 329, September, 2003.
[15]T. Ohtou, T. Nagumo, and T. Hiramoto, "Variable Body Effect Factor FD SOI MOSFET for Ultra-Low Power VTCMOS Applications", 2003 International Conference on Solid State Devices and Materials (SSDM), Keio Plaza Hotel, pp. 272 - 273, September, 2003.
[14]T. Nagumo, and T. Hiramoto, "Current Drive Improvement by Enhanced Body Effect Factor Due to Finite Inversion Layer Thickness in Variable Threshold Voltage CMOS", 2002 International Conference on Solid State Devices and Materials (SSDM), Nagoya Congress Center, pp. 798 - 799, September, 2002.
[13]T. Hiramoto (Invited), "Future Electron Devices and SOI Technology", 2002 International Conference on Solid State Devices and Materials (SSDM), Nagoya Congress Center, pp. 780 - 781, September, 2002.
[12]Q. Liu, T. Sakurai, and T. Hiramoto, "Optimum Device Consideration for Standby Power Reduction Scheme Using Drain Induced Barrier Lowering (DIBL)", 2002 International Conference on Solid State Devices and Materials (SSDM), Nagoya Congress Center, pp. 258 - 259, September, 2002.
[11]M. Saitoh, H. Majima, and T. Hiramoto, "Tunneling Barrier Structure in Room-Temperature Operating Silicon Single-Electron and Single-Hole Transistors", 2002 International Conference on Solid State Devices and Materials (SSDM), Nagoya Congress Center, pp. 108 - 109, September, 2002.
[10]Takashi Inukai, Hyunsik Im, and Toshiro Hiramoto, "Origin of Critical Substrate Bias in Variable Threshold Voltage CMOS", 2001 International Conference on Solid State Devices and Materials (SSDM), Diamond Hotel, Tokyo, pp. 106 - 107, September, 2001.
[9]T. Hiramoto (Invited), "Optimum Device Parameters and Scalability of Variable Threshold CMOS (VTCMOS)", 2000 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, pp. 372 - 373, August, 2000.
[8]H. Koura, M. Takamiya, and T. Hiramoto, "Optimum Conditions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs", 1999 International Conference on Solid State Devices and Materials (SSDM'99), Tokyo, Japan, pp. 446 - 447, September, 1999.
[7]T. Inukai and T. Hiramoto, "Suppression of Stand-by Tunnel Current in Ultra-Thin-Gate Oxide MOSFETs by Dual Oxide Thickness MTCMOS (DOT-MTCMOS)", 1999 International Conference on Solid State Devices and Materials (SSDM'99), Tokyo, Japan, pp. 264 - 265, September, 1999.
[6]N. Takahashi, H. Ishikuro, and T. Hiramoto, "Characteristics of Silicon Single Electron Transistors Controlled by Charge Injection into Silicon Nano-Crystal Floating Dots", 1999 International Conference on Solid State Devices and Materials (SSDM'99), Tokyo, Japan, pp. 236 - 237, September, 1999.
[5]Tran Ngoc Duyet, Hiroki Ishikuro, Yi Shi, Takuya Saraya, Makoto Takamiya, and Toshiro Hiramoto, "Measurement of Energetic and Lateral Distribution of Interface State Density in FD SOI MOSFETs", 1998 International Conference on Solid State Devices and Materials (SSDM'98), International Conference Center Hiroshima, Hiroshima, Japan, pp. 322 - 323, September, 1998.
[4]Makoto Takamiya, Takuya Saraya, Tran Ngoc Duyet, Yuri Yasuda, and Toshiro Hiramoto, "High Performance Accumulated Back-Interface Dynamic Threshold SOI MOSFET's (AB-DTMOS) with Large Body Effect at Low Supply Voltage", 1998 International Conference on Solid State Devices and Materials (SSDM'98), International Conference Center Hiroshima, Hiroshima, Japan, pp. 312 - 313, September, 1998. This paper received the SSDM Young Researcher Award.
[3]Yi Shi, Kenichi Saito, Hiroki Ishikuro, and Toshiro Hiramoto, "Characteristics of Narrow Channel MOSFET Memory Based on Silicon Nanocrystals", 1998 International Conference on Solid State Devices and Materials (SSDM'98), International Conference Center Hiroshima, Hiroshima, Japan, pp. 172 - 173, September, 1998.
[2]T. Saraya, M. Takamiya, T.N. Duyet, and T. Hiramoto, "New Measurement Technique of Sub-Bandgap Impact Ionization Current by Transient Characteristics of Partially Depleted SOI MOSFETs", 1997 International Conference on Solid State Devices and Materials (SSDM'97), Act City Hamamatsu, Hamamatsu, Japan, pp. 554 - 555, September, 1997.
[1]H. Ishikuro, T. Saraya, T. Hiramoto, and T. Ikoma, "Extremely Large Amplitude of Random Telegram Signals in a Very Narrow Split-Gate MOSFET at Low Temperatures", International Conference on Solid State Devices and Materials (SSDM), pp. 342 - 345, Osaka, Japan, August, 1995.

52 Papers in Silicon Nanoelectronics Workshop

[55]Ki-Hyun Jang, Takuya Saraya, Masaharu Kobayashi, Naomi Sawamoto, Atsushi Ogura, and Toshiro Hiramoto, “Characteristics Variability of Gate-All-Around Polycrystalline Silicon Nanowire Transistors with Width of 10nm Scale”, Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, pp. 33 - 34, June 4, 2017.
[54]Kyungmin Jang. Nozomu Ueyama, Masaharu Kobayashi, and Toshiro Hiramoto, “Investigations on Dynamic Characteristics of Ferroelectric HfO2 Based on Multi-Domain Interaction Model”, Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, pp. 15 - 16, June 4, 2017.
[53]Daiki Ueda Kiyoshi Takeuchi, Masaharu Kobayashi, and Toshiro Hiramoto, “Carrier-Separated Equivalent Circuit Modeling for Steep Subthreshold Slope PN-Body Tied SOI FET”, Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, pp. 13 - 14, June 4, 2017.
[52]Kyungmin Jang, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “On Gate Stack Scalability of Double-Gate Negative-Capacitance FET with Ferroelectric HfO2 for Energy-Efficient Sub-0.2V Operation”, IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 176 - 177, June 13, 2016.
[51]Masaharu Kobayashi, Kyungmin Jang, Nozomu Ueyama, and Toshiro Hiramoto, “Negative Capacitance as a Performance Booster for Tunnel FET”, IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 150 - 151, June 13, 2016.
[50]Toshiro Hiramoto, Kiyoshi Takeuchi, and Masaharu Kobayashi (Invite), “Ultra-Low Power and Ultra-Low Voltage Devices and Circuits for IoT Applications”, IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 146 - 147, June 13, 2016.
[49]Tomoko Mizutani, Kiyoshi Takeuchi, Ryota Suzuki, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “Increased Drain-Induced Variability and Within-Device Variability in Extremely Narrow Silicon Nanowire MOSFETs with Width down to 2nm”, IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 138 - 139, June 13, 2016.
[48]T. Mizutani, Y. Tanahashi, R. Suzuki, T. Saraya, M. Kobayashi, and T. Hiramoto, “Threshold Voltage and Current Variability of Extremely Narrow Silicon Nanowire MOSFETs with Width down to 2nm”, Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, pp. 21 - 22, June 14, 2015.
[47]Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, and Toshiro Hiramoto, "Statistical Analysis of Minimum Operation Voltage (Vmin) in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells", IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 166 - 167, June 9, 2014.
[46]Seung-Min Jung, Takuya Saraya, and Toshiro Hiramoto, "Analysis of Delay Time in Subthreshold CMOS Circuits Operating at Ultra-Low Supply Voltage", IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 87 - 88, June 9, 2014.
[45]Nurul Ezaila Alias, Tomoko Mizutani, Anil Kumar, Takuya Saraya, and Toshiro Hiramoto, "Recovery and Permanent Components of |Vth| Shifts in pFETs by High-Voltage ON-state Stress", IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 81 - 82, June 8, 2014.
[44]Hitoshi Ohno, Tomoko Mizutani, Takuya Saraya, and Toshiro Hiramoto, "Comparison of Statistical Distributions of Random Telegraph Noise (RTN) in Subthreshold Region and Strong Inversion Region", IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 33 - 34, June 8, 2014.
[43]Nurul Ezaila Alias, Anil Kumar, Takuya Saraya, Shinji Miyano, and Toshiro Hiramoto, "Variability and Recovery Behaviors of |Vth| Shift of pFETs by High-Voltage OFF-State and ON-State Stress for Post-Fabrication SRAM Cell Stability Self-Improvement", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 33 - 34, June 9, 2013.
[42]Anil Kumar, Takuya Saraya1, Shinji Miyano, and Toshiro Hiramoto, "SRAM Cell Stability Parameter: Noise Margin or Vmin?", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 31 - 32, June 9, 2013.
[41]T. Mizutani, Y. Yamamoto, H. Makiyama, H. Shinohara, T. Iwamatsu, H. Oda, N. Sugii, and T. Hiramoto, "Reduced Cell Current Variability in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells at Supply Voltage of 0.4V", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 29 - 30, June 9, 2013.
[40]Seung-Min Jung, Tomoko Mizutani, and Toshiro Hiramoto, "Impact of Drain-Induced Barrier Lowering on Ultra-Low Supply Voltage CMOS Circuits Operating in Subthreshold Region", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 23 - 24, June 9, 2013.
[39]T. Mizutani, Y. Yamamoto, H. Makiyama, T. Tsunomura, T. Iwamatsu, H. Oda, N. Sugii, and T. Hiramoto, "Reduced Drain Current Variability in Fully Depleted Silicon-on-Thin-BOX (SOTB) MOSFETs", IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 71 - 72, June 11, 2012.
[38]Ryota Suzuki, Motoki Nozue, Takuya Saraya, and Toshiro Hiramoto, "Reinvestigation of Dot Formation Mechanisms in Silicon Nanowire Channel Single-Electron/Hole Transistors Operating at Room Temperature", IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 57 - 58, June 11, 2012.
[37]Anil Kumar, Takuya Saraya, Shinji Miyano, and Toshiro Hiramoto, "Self-Improvement of Cell Stability in SRAM by Post Fabrication Technique", IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 79 - 80, June 10, 2012.
[36]A. Kumar, T. Mizutani, T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Mogami, T. Hiramoto , "Statistical Analysis of DIBL and Current-Onset Voltage (COV) Variability in Scaled MOSFETs", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 13 - 14, June 12, 2011.
[35]T. Mizutani, A. Kumar, T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Mogami, and T. Hiramoto , "Evaluation of Variability in High-k/Metal-Gate MOSFETs Using Takeuchi Plot", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 11 - 12, June 12, 2011.
[34]T. Mizutani, A. Kumar, T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, "Statistic Characteristics of "Current-Onset Voltage" in Scaled MOSFETs Analyzed by 8k DMA TEG", IEEE Silicon Nanoelectronics Workshop, J Hilton Hawaiian Village, HI. USA, pp. 81 - 82, June 13, 2010.
[33]A. Kumar, T. Mizutani, K. Shimizu, T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, "Origin of "Current-Onset Voltage" Variability in Scaled MOSFETs", IEEE Silicon Nanoelectronics Workshop, J Hilton Hawaiian Village, HI. USA, pp. 7 - 8, June 13, 2010.
[32]Ryota Suzuki, Yeon-Joo Jeong, Takuya Saraya, and Toshiro Hiramoto, "Automatic Characteristics Control of Single-Electron Transistors in Collaboration with CMOS Digital Circuits" Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 157 - 158, June 14, 2009.
[31]Ichiro Yamato, Arifin Tamsir Putra, and Toshiro Hiramoto, "Impact of Lateral Dopant Profile on Threshold Voltage Variability in Scaled MOSFETs", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 35 - 36, June 13, 2009.
[30]Yeon Joo Jeong, Kousuke Miyaji, and Toshiro Hiramoto, "Experimental Study on Silicon Nanowire nMOSFET and Single-Electron Transistor at Room Temperature under Uniaxial Tensile Strain", IEEE Silicon Nanoelectronics Workshop, M0930, Hilton Hawaiian Village, HI, USA, June 16, 2008.
[29]Arifin Tamsir Putra, Takaaki Tsunomura, Akio Nishida , Shiro Kamohara, Kiyoshi Takeuchi, and Toshiro Hiramoto, "Impact of Atomic Oxide Roughness and Local Gate Depletion on Vth Variation in MOSFETs", IEEE Silicon Nanoelectronics Workshop, S1205, Hilton Hawaiian Village, HI, USA, June 15, 2008.
[28]Ken Shimizu and Toshiro Hiramoto, "Hole Mobility Enhancement by [110] Uniaxial Compressive Strain in (110) Oriented Ultra-Thin Body pFETs with SOI Thickness of Less Than 4 nm", IEEE Silicon Nanoelectronics Workshop, S1135, Hilton Hawaiian Village, HI, USA, June 15, 2008.
[27]J. S. Park, T. Saraya, K. Miyaji, K. Shimizu, A. Higo, K. Takahashi, Y. Yi, H. Toshiyoshi, and T. Hiramoto, "Characteristic Modulation of Silicon MOSFETs and Single Electron Transistors with a Movable Gate Electrode", IEEE Silicon Nanoelectronics Workshop, S1015, Hilton Hawaiian Village, HI, USA, June 15, 2008.
[26]Keisuke Takahashi, Tetsu Ohtou, Arifin Tamsir Putra, Ken Shimizu, and Toshiro Hiramoto, "Body Factor and Leakage Current Reduction in Bulk FinFETs", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 95 - 97, June, 2007.
[25]Arifin Tamsir Putra, Akio Nishida, Shiro Kamohara and Toshiro Hiramoto, "Random Vth Variation Induced by Gate Edge Fluctuations in Nanoscale MOSFETs", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 73 - 74, June, 2007.
[24]S. Lee, K. Miyaji, M. Kobayashi, and T. Hiramoto, "Novel Long-Range-Extension of Coulomb Blockade Region in Room-Temperature Operating Silicon Single-Hole Transistor", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 115 - 116, June, 2007.
[23]Arifin Tamsir Putra, Tetsu Ohtou, and Toshiro Hiramoto, "Critical Substrate Bias in Variable-Threshold Voltage CMOS with Short Channel FD SOI MOSFETs",IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI, USA, pp. 159 - 160, June, 2006.
[22]K. Shimizu, G. Tsutsui, D. Januar, T. Saraya and T. Hiramoto, "Experimental Study on Breakdown of Mobility Universality in <100>-Directed (110)-Oriented pMOSFETs",IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI, USA, pp. 11 - 12, June, 2006.
[21]Tetsu Ohtou, Nobuyuki Sugii, and Toshiro Hiramoto, "Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully-Depleted SOI MOSFETs with Extremely Thin BOX",IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI, USA, pp. 15 - 16, June, 2006.
[20]K. Yokoyama, T. Nagumo, T. Ohtou, and T. Hiramoto, "Experimental Demonstration of Variable Body Factor FD SOI MOSFET with Thin Buried Oxide", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 78 - 79, June, 2005.
[19]Kosuke Yanagidaira, Masumi Saitoh, and Toshiro Hiramoto, "FinFET-Type Silicon Nanocrystal Memories with Ultranarrow Channel", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 100 - 101, June, 2005.
[18]Kousuke Miyaji, Masumi Saitoh, and Toshiro Hiramoto, "Analytical Model for Room-Temperature Operating Silicon Single-Electron Transistors with Discrete Quantum Energy Levels", Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, pp. 82 - 83, June, 2005.
[17]Kosuke Yanagidaira, Masumi Saitoh, and Toshiro Hiramoto, "Performance Improvements in Silicon Nanocrystal Memories with Ultra-Thin-Body Double-Gate Structure", Hilton Hawaiian Village, Honolulu, HI, USA, pp. 141 - 142, June 2004.
[16]Hidehiro Harata, Masumi Saitoh, and Toshiro Hiramoto, "Silicon Single-Hole Transistor with Large Coulomb Blockade Oscillations and High Voltage Gain at Room Temperature", IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI, USA, pp. 81 - 82, June 2004.
[15]Toshiharu Nagumo and Toshiro Hiramoto, "Reverse Short Channel Effect of Body Factor in Highly-Doped Low-Fin FETs by Corner Effect", IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI, USA, pp.67 - 68, June 2004.
[14]Gen Tsutsui, Masumi Saitoh, Toshiharu Nagumo, and Toshiro Hiramoto, "Impact of SOI Thickness Fluctuation on Threshold Voltage Variation in Ultra Thin Body SOI MOSFETs", IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI, USA, pp. 25 - 26, June 2004.
[13]Julien Brault, Masumi Saitoh, and Toshiro Hiramoto, "Channel Width and Length Dependence in Si Nano-Crystal Memories with Ultra Nano-Scale Channel", IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI, USA, pp. 103 - 104, June 2004.
[12]M. Saitoh, T. Murakami, and T. Hiramoto, "Large Coulomb Blockade Oscillations at Room Temperature in Ultra-Narrow Wire Channel MOSFETs Formed by Slight Oxidation Process", 2003 Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, Japan, pp. 76 - 77, June, 2003.
[11]G. Tsutsui, T. Nagumo, and T. Hiramoto, "Enhancement of Adjustable Threshold Voltage Range by Substrate Bias Due to Quantum Confinement in Ultra Thin Body pMOSFETs", 2003 Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, Japan, pp. 6 - 7, June, 2003.
[10]M. Saitoh, T. Murakami, and T. Hiramoto, "Effects of Oxidation Process on the Tunneling Barrier Height in Room-Temperature Operating Silicon Single-Electron Transistors", IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI, USA, pp. 59 - 60, June, 2002.
[9]M. Saitoh, T. Saito, T. Inukai, and T. Hiramoto, "Transport Spectroscopy of the Silicon Quantum Dot in a Single-Electron Transistor", 2001Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, pp. 36 - 37, June, 2001.
[8]Toshiki Saito, Takuya Saraya, Takashi Inukai, Hideaki Majima, and Toshiro Hiramoto, "Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs", 2001 Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, pp. 6 - 7, June, 2001.
[7]Y. Yasuda, M. Takamiya, and T. Hiramoto, "Threshold Voltage Fluctuations Induced by Statistical "Position" and "Number" Impurity Fluctuations in Bulk MOSFETs", 2000 Silicon Nanoelectronics Workshop, Hawaii, USA, pp. 40 - 41, June, 2000.
[6]Y. Yasuda, M. Takamiya, and T. Hiramoto, "Effects of Impurity Position Distribution on Threshold Voltage Fluctuations in Scaled MOSFETs", 1999 Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, Japan, pp. 86 - 87, June, 1999.
[5]H. Majima, H. Ishikuro, and T. Hiramoto, "Threshold Voltage Shift in Ultra-Narrow MOSFETs by Quantum Mechanical Narrow Channel Effect", 1999 Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, Japan, pp. 76 - 77, June , June, 1999.
[4]Y. Shi, H. M. Bu, X. L. Yuan, Y. D. Zheng, H. Ishikuro, H. Majima, and T. Hiramoto, "Random Telegraph Signals in Very Narrow Channel MOSFET", 1999 Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, Japan, pp. 28 - 29, June, 1999.
[3]K. Saito, Y. Shi, H. Ishikuro, and T. Hiramoto, "Narrow Channel MOS Memory Based on Silicon Nano-Crystals", 1998 IEEE Silicon Nanoelectronics Workshop, Hawaii, USA, pp. 17 - 18, June, 1998.
[2]Hiroki Ishikuro and Toshiro Hiramoto, "Fabrication of Si Point Contact MOSFETs Acting as Single Electron Transistors at Room Temperature", Silicon Nanoelectronics Workshop 1997, Rihga Royal Hotel Kyoto, Kyoto, Japan, pp. 64 - 65, June, 1997.
[1]T. Hiramoto, H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, and T. Ikoma, "Room Temperature Operation of Single Electron Transistors Fabricated by LSI-Compatible Anisotropic Etching Process on SOI Substrates", Silicon Nanoelectronics Workshop, Honolulu, Hawaii, USA, June, 1996.

Two Papers in ICMTS

[2]Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto, and Hirofumi Shinohara, “Measurement of SRAM Power-Up State for PUF Applications using an Addressable SRAM Cell Array Test Structure”, 29th IEEE International Conference on Microelectronic Test Structures (ICMTS), Mielparque Yokohama, pp. 130 - 133, March 30, 2016.
[1]Hao Qiu, Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “A New Write Stability Metric Using Extended Write Butterfly Curve for Yield Estimation in SRAM Cells at Low Supply Voltage”, 29th IEEE International Conference on Microelectronic Test Structures (ICMTS), Mielparque Yokohama, pp. 126 - 129, March 30, 2016.

Four Papers in ISLPED

[4]Toshiro Hiramoto (Invited), "Ultra-Low-Voltage Operation: Device Perspective", Special Session on Ultra-Low Voltage Operation, International Symposium on Low Power Electronics and Design (ISLEPD), Fukuoka Convention Center, Fukuoka, August 1, 2011.
[3]Hyunsik Im, M. Song, T. Hiramoto, and T. Sakurai, "Physical Insight Into Fractional Power Dependence of Saturation Current on Gate Voltage in Advanced Short Channel MOSFETs (Alpha-Power Law Model)", 2002 International Symposium on Low Power Electronics and Design (ISLPED'02), Monterey Beach Hotel Resort, CA, USA, pp. 13 - 18, August, 2002.
[2]Takashi Inukai, Toshiro Hiramoto, and Takayasu Sakurai, "Variable Threshold Voltage CMOS (VTCMOS) in Series Connected Circuits", 2001 International Symposium on Low Power Electronics and Design, Hilton Waterfront Beach Resort, Huntington Beach, CA, USA, pp. 201 - 206, August, 2001.
[1]Hyunsik Im, T. Inukai, H. Gomyo, T. Hiramoto, and T. Sakurai, "VTCMOS Characteristics and Its Optimum Conditions Predicted by a Compact Analytical Model", 2001 International Symposium on Low Power Electronics and Design, Hilton Waterfront Beach Resort, Huntington Beach, CA, USA, pp. 123 - 128, August, 2001.

One Paper in IEEE-NANO

[1]Masumi Saitoh and Toshiro Hiramoto, "Suppression of Series Parasitic Resistance and Observation of Quantum Effects in a Silicon Single-Electron Transistor", The First IEEE Conference on Nanotechnology, Outrigger Wailea Resort, Maui, Hawaii, USA, pp. 243 - 247, October, 2001.

One Paper in NanoMES

[1]Yuta Saito, Masumi Saitoh, Kosuke Yanagidaira, Hideaki Majima, and Toshiro Hiramoto, "Experimental Demonstration of Quantum Mechanical Narrow Channel Effect in <100>-Oriented Ultra-Narrow Channel MOSFETs", Fourth International Symposium on Nanostructures and Mesoscopic Systems (NanoMES2003), Tempe Mission Palms Hotel, Tempe, Arizona, USA, FP3, February, 2003.

Four Papers in SISPAD

[4]Kiyoshi Takeuchi, Akio Nishida, and Toshiro Hiramoto (Invited), "Random Fluctuations in Scaled MOS Devices", International Conference on Simulation of Semiconductor Devices and Processes (SISPAD), Hotel del Coronado, San Diego, California, USA, September 10, 2009.
[3]A.T. Putra, T. Tsunomura, A. Nishida, S. Kamohara, K. Takeuchi, and T. Hiramoto, "Impact of Fixed Charge at MOSFETs' SiO2/Si Interface on Vth Variation", to be presented in International Conference on Simulation of Semiconductor Devices and Processes (SISPAD), Hakone Prince Hotel, Kanagawa, Japan, September 9, 2008.
[2]Toshiro Hiramoto, Kousuke Miyaji, and Masaharu Kobayashi (invited), "Transport in Silicon Nanowire and Single-Electron Transistor", International Conference on Simulation of Semiconductor Devices and Processes (SISPAD), Vienna University of Technology, Vienna, Austria, pp. 209 - 215, September 27, 2007.
[1]T. Hiramoto and H. Majima (Invited), "Characteristics and Simulations of Silicon Nano-Scale MOSFETs", 2000 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Seattle, USA, pp. 179 - 183, September, 2000

Two Papers in ICPS

[2]Hiroki Ishikuro and Toshiro Hiramoto, "The Origin of Tunnel Barrier in Silicon Single Electron Transistor", International Conference on Physics of Semiconductors, Mo-P140, Jerusalem, Israel, August, 1998.
[1]H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, T. Hiramoto, and T. Ikoma, "Coulomb Blockade in a Weakly Coupled Multiple-Dot-Channel MOSFET", International Conference on Physics of Semiconductors, Berlin, Germany, July, 1996.

One Paper in DRC

[1]Hiroki Ishikuro and Toshiro Hiramoto, "Energy Spectrum of the Quantum-Dot in a Si Single-Electron-Device", IEEE 55th Annual Device Research Conference, Colorado State University, Fort Collins, Colorado, USA, pp. 84 - 85, June, 1997.

Three Papers in MNC

[3]Toshiro Hiramoto (Plenary), "Silicon VLSI Device Technology and Nanoelectronics", 20th International Microprocesses and Nanotechnology Conference (MNC), Kyoto International Conference Center, p. 6 - 7, November 6, 2007.
[2]E. Nagata, N. Takahashi, H. Ishikuro, and T. Hiramoto, "Characteristics Distribution of Narrow Channel MOSFET Memories with Silicon Nano-Crystal Floating Gates", 1999 International Microprocesses and Nanotechnology Conference, Yokohama Ginou Bunka Kaikann, Yokohama, Japan, pp. 86 - 87, July, 1999.
[1]T. Hiramoto, H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, and T. Ikoma, "Fabrication of Si Nano-Structures by Anisotropic Etching for Single Electron Device Applications", 9th International MicroProcess Conference, Kitakyushu International Conference Center, Fukuoka, Japan, July, 1996.

15 Papers in ISDRS

[16]Kyungmin Jang, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “Ion/Ioff Ratio Enhancement of Gate-All-Around Nanowire Negative-Capacitance FET with Ferroelectric HfO2”, International Semiconductor Device Research Symposium (ISDRS), Hyatt Regency Bethesda, MD, USA, December 9, 2016.
[15]Makoto Suzuki, Takuya Saraya, Ken Shimizu, Takayasu Sakurai, and Toshiro Hiramoto, "Improvement of Static Noise Margin in SRAM by Post-Fabrication Self-Convergence Technique", International Semiconductor Device Research Symposium (ISDRS), TP7-03, University of Maryland, Collage Park, MD, USA, December 10, 2009.
[14]Ichiro Yamato, Tatsuya Mama, Takaaki Tsunomura, Akio Nishida, and Toshiro Hiramoto, "Anomalous Back-Bias Dependence of Threshold Voltage Variability in NMOSFETs Due to High Concentration Regions near Source and Drain", International Semiconductor Device Research Symposium (ISDRS), WP5-04, University of Maryland, Collage Park, MD, USA, December 9, 2009.
[13] Jiezhi Chen, Takuya Saraya, Toshiro Hiramoto, "Experimental Study on Uniaxially Stressed Gate-All-Around Silicon Nanowires n-MOSFETs on (110) Silicon-On-Insulator", International Semiconductor Device Research Symposium (ISDRS), WP5-06, University of Maryland, Collage Park, MD, USA, December 9, 2009.
[12]Toshiro Hiramoto, Gen Tsutsui, Ken Shimizu, and Masaharu Kobayashi (Invited), "Transport in Ultra-Thin-Body SOI and Silicon Nanowire MOSFETs", International Semiconductor Device Research Symposium (ISDRS), University of Maryland, College Park, MD, USA, TA6-02, December 13, 2007.
[11]Keisuke Takahashi, Arifin Tamsir Putra, and Toshiro Hiramoto, "FinFETs with Both Large Body Factor and High Drive-Current", International Semiconductor Device Research Symposium (ISDRS), University of Maryland, College Park, MD, USA, WP9-01-11, December 12, 2007.
[10]A.T. Putra, A. Nishida, S. Kamohara, T. Tsunomura, and T. Hiramoto, "Impact of Local Poly-Si Gate Depletion on Vth Variation in Nanoscale MOSFETs Investigated by 3D Device Simulation", International Semiconductor Device Research Symposium (ISDRS), University of Maryland, College Park, MD, USA, WP8-03, December 12, 2007.
[9]Masaharu Kobayashi, Kousuke Miyaji, Masumi Saitoh, and Toshiro Hiramoto, "Large Temperature Dependence of Negative Differential Conductance in Room-Temperature Operating Silicon Single-Electron/Single-Hole Transistor", International Semiconductor Device Research Symposium, Bethesda, MD, USA, TP3-03, December, 2005.
[8]Kousuke Miyaji, Masaharu Kobayashi, Tetsu Ohtou, and Toshiro Hiramoto, "On the Accuracy of Analytical Model for Room-Temperature Operating Silicon Single-Electron Transistors with Discrete Quantum Energy Levels", International Semiconductor Device Research Symposium, Bethesda, MD, USA, WP7-07-06, December, 2005.
[7]A. Tamsir P., T. Ohtou, T. Nagumo and T. Hiramoto, "Critical Substrate Bias in Variable Threshold Voltage CMOS (VTCMOS) Scheme with Short Channel Devices", International Semiconductor Device Research Symposium, Bethesda, MD, USA, WP7-08-04, December, 2005.
[6]Toshiharu Nagumo and Toshiro Hiramoto, "Design Guideline of Multi-Gate MOSFETs Considering Body Effect", International Semiconductor Device Research Symposium, Bethesda, MD, USA, TP6-04, December, 2005.
[5]Anil Kumar, Toshiharu Nagumo, Gen Tsutsui, and T. Hiramoto, "Analytical Expression of Body Factor in Short Channel Bulk MOSFETs", 2003 International Semiconductor Device Research Symposium (ISDRS), Washington DC, USA, pp. 476 - 477, December, 2003.
[4]G. Tsutsui, M. Saitoh, T. Nagumo, and T. Hiramoto, "Experimental Study on the Mobility Universality in Ultra Thin Body SOI pMOSFETs", 2003 International Semiconductor Device Research Symposium (ISDRS), Washington DC, USA, pp.361 - 362, December, 2003.
[3]T. Hiramoto, T. Nagumo, and T. Ohtou(Invited), "Low-Power Device Design of Fully-Depleted SOI MOSFETs", 2003 International Semiconductor Device Research Symposium (ISDRS), Washington DC, USA, pp. 388 - 389, December, 2003.
[2]Makoto Takamiya, Yuri Yasuda, and Toshiro Hiramoto, "Deep Sub-0.1µm Fully Depleted SOI MOSFET's with Ultra-Thin Silicon Film and Thick Buried Oxide for Low-Power Applications", Proceedings of 1997 International Semiconductor Device Research Symposium, Charlottesville, Virginia, USA, pp. 215 - 218, December, 1997.
[1]T. Hiramoto (Invited), "Future Trend of Scaled LSI Devices and Single Electronics", 1995 International Semiconductor Device Research Symposium (ISDRS), pp. 801 - 802, Charlottesville, Virginia, USA, December, 1995.

Five Papers in QDS

[5]H. N. Wang, N. Takahashi, H. Majima, T. Inukai, and T. Hiramoto, "Device Parameters for Electron Number Control in MOSFET Memories Based on Silicon Nanocrystal Floating Dots", 2000 International Symposium on Formation, Physics and Device Application of Quantum Dot Structures, p. 116, Sapporo, Japan, September, 2000.
[4]T. Hiramoto, N. Takahashi, H. Ishikuro, and M. Saitoh, "Large Electron Addition Energy above 250 meV in the Silicon Quantum Dot in a Single Electron Transitor", 2000 International Symposium on Formation, Physics and Device Application of Quantum Dot Structures, p. 4, Sapporo, Japan, September, 2000.
[3]Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, "Effects of Interface Traps on Charge Retention Characteristics in Silicon-Quantum-Dot-Based MOS Diodes", 1998 International Symposium on Formation, Physics and Device Application of Quantum Dot Structures, p. 76, Sapporo, Japan, June, 1998.
[2]H. Ishikuro and T. Hiramoto, "Fabrication of Nano-Scale Point Contact MOSFETs Using Micrometer-Scale Design Rule", 1998 International Symposium on Formation, Physics and Device Application of Quantum Dot Structures, p. 6, Sapporo, Japan, June, 1998.
[1]T. Hiramoto, H. Ishikuro, T. Fujii, G. Hashiguchi, and T. Ikoma, "Room Temperature Coulomb Blockade and Low Temperature Hopping Transport in a Multiple-Dot-Channel MOSFET", 1996 International Symposium on Formation, Physics and Device Application of Quantum Dot Structures, p. 142, Sapporo, Japan, November, 1996.

One Paper in QFD

[1]M. Saitoh and T. Hiramoto, "Effects of Quantum Level Spacing on Transport in Silicon Single Electron Transistors with an Ultra-Small Quantum Dot", 4th International Workshop on Quantum Functional Devices, pp. 136 - 137, Kanazawa, Japan, November, 2000.

Two Papers in ICICDT

[2]Toshiro Hiramoto and Toshiharu Nagumo (Invited), "Multi-Gate MOSFETs with Back-Gate Control", 2006 International Conference on Integrated Circuit Design and Technology (ICICDT), pp. 80 - 81, May, 2006.
[1]Toshiro Hiramoto (Invited), "Advanced Device Structure for Aggressively Scaled MOSFETs", 2004 International Conference on Integrated Circuit Design and Technology, Austin, TX, USA, pp. 59 - 64, May, 2004.